Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 89 of 92
POWER-ON RESET OPERATION
An internal power-on reset (POR) is implemented on the
ADuC7128/ADuC7129. For LV
DD
below 2.45 V, the internal
POR holds the ADuC7128/ADuC7129 in reset. As LV
DD
rises
above 2.45 V, an internal timer times out for typically 64 ms
before the part is released from reset. The user must ensure that
the power supply, IOV
DD
, has reached a stable 3.0 V minimum
level by this time. On power-down, the internal POR holds the
ADuC7128/ADuC7129 in reset until LV
DD
has dropped below
2.45 V. Figure 72 illustrates the operation of the internal POR
in detail.
IOV
DD
3.3
V
2.6V
2.4V TYP2.4V TYP
64ms TYP
LV
DD
POR
MRST
0.12ms TYP
06020-062
Figure 72. Internal Power-On Reset Operation