Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 70 of 92
Table 96. Element Input/Output
PLA Block 0 PLA Block 1
Element Input Output Element Input Output
0 P1.0 P1.7 8 P3.0 P4.0
1 P1.1 P0.4 9 P3.1 P4.1
2 P1.2 P0.5 10 P3.2 P4.2
3 P1.3 P0.6 11 P3.3 P4.3
4 P1.4 P0.7 12 P3.4 P4.4
5 P1.5 P2.0 13 P3.5 P4.5
6 P1.6 P2.1 14 P3.6 P4.6
7 P0.0 P2.2 15 P3.7 P4.7
PLA MMRs Interface
The PLA peripheral interface consists on 21 MMRs, as shown
in
Table 97.
Table 97. PLA MMRs
Name Description
PLAELMx
Element 0 to Element 15 Control Registers.
Configure the input and output mux of each
element, select the function in the look-up table,
and bypass/use the flip-flop.
PLACLK
Clock Selection for the Flip-Flops of Block 0 and
Clock Selection for the Flip-Flops of Block 1.
PLAIRQ Enable IRQ0 and/or IRQ1. Select the source of the IRQ.
PLAADC PLA Source from ADC Start Conversion Signal.
PLADIN Data Input MMR for PLA.
PLAOUT
Data Output MMR for PLA. This register is always
updated.
A PLA tool is provided in the development system to easily
configure the PLA.
Table 98. PLAELMx MMR Bit Designations
Bit Value PLAELM0
PLAELM1 to
PLAELM7
PLAELM8
PLAELM9 to
PLAELM15
Description
31:11 Reserved.
00 Element 15 Element 0 Element 7 Element 8 Mux (0) Control. Select feedback source.
01 Element 2 Element 2 Element 10 Element 10
10 Element 4 Element 4 Element 12 Element 12
10:9
11 Element 6 Element 6 Element 14 Element 14
00 Element 1 Element 1 Element 9 Element 9 Mux (1) Control. Select feedback source.
01 Element 3 Element 3 Element 11 Element 11
10 Element 5 Element 5 Element 13 Element 13
8:7
11 Element 7 Element 7 Element 15 Element 15
6 Mux (2) Control.
Set by user to select the output of Mux (0).
Cleared by user to select the bit value from PLADIN.
5
Mux (3) Control.
Set by user to select the input pin of the particular element.
Cleared by user to select the output of Mux (1).
4:1 Look-Up Table Control.
0000 0
0001 NOR
0010 B AND NOT A
0011 NOT A
0100 A AND NOT B
0101 NOT B
0110 EXOR
0111 NAND
1000 AND
1001 EXNOR
1010 B
1011 NOT A OR B
1100 A
1101 A OR NOT B
1110 OR
1111 1
0 Mux (4) Control.
Set by user to bypass the flip-flop.
Cleared by user to select the flip-flop.
Cleared by default.