Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 69 of 92
I2CxFIF Register
Name Address Default Value Access
I2C0FIF 0xFFFF084C 0x0000 R
I2C1FIF 0xFFFF094C 0x0000 R
I2CxFIF is a FIFO status register.
Table 95. I2C0FIF MMR Bit Designations
Bit Value Description
15:10 Reserved.
9 Master Transmit FIFO Flush.
Set by user to flush the master Tx FIFO.
Cleared automatically once the master Tx FIFO is flushed. This bit also flushes the slave receive FIFO.
8 Slave Transmit FIFO Flush.
Set by user to flush the slave Tx FIFO.
Cleared automatically once the slave Tx FIFO is flushed.
7:6 Master Rx FIFO Status Bits.
00 FIFO Empty.
01 Byte Written to FIFO.
10 1 Byte in FIFO.
11 FIFO Full.
5:4 Master Tx FIFO Status Bits.
00 FIFO Empty.
01 Byte Written to FIFO.
10 1 Byte in FIFO.
11 FIFO Full.
3:2 Slave Rx FIFO Status Bits.
00 FIFO Empty.
01 Byte Written to FIFO.
10 1 Byte in FIFO.
11 FIFO Full.
1:0 Slave Tx FIFO Status Bits.
00 FIFO Empty.
01 Byte Written to FIFO.
10 1 Byte in FIFO.
11 FIFO full.
PROGRAMMABLE LOGIC ARRAY (PLA)
The ADuC7128/ADuC7129 integrate a fully programmable
logic array (PLA) that consists of two independent but
interconnected PLA blocks. Each block consists of eight PLA
elements, giving a total of 16 PLA elements.
A PLA element contains a two input look-up table that can be
configured to generate any logic output function based on two
inputs and a flip-flop as represented in
Figure 54.
4
2
0
1
3
A
B
LOOK-UP
TABLE
06020-049
Figure 54. PLA Element
In total, 30 GPIO pins are available on the ADuC7128/ADuC7129
for the PLA. These include 16 input pins and 14 output pins.
They need to be configured in the GPxCON register as PLA
pins before using the PLA. Note that the comparator output is
also included as one of the 16 input pins.
The PLA is configured via a set of user MMRs and the output(s)
of the PLA can be routed to the internal interrupt system, to the
CONVST
signal of the ADC, to an MMR, or to any of the
16 PLA output pins.
The interconnection between the two blocks is supported by
connecting the output of Element 7 of Block 1 fed back to the
Input 0 of Mux 0 of Element 0 of Block 0, and the output of
Element 7 of Block 0 is fed back to the Input 0 of Mux 0 of
Element 0 of Block 1.