Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 68 of 92
Bit Description
7 Master Serial Clock Enable Bit.
Set by user to enable generation of the serial clock in master mode.
Cleared by user to disable serial clock in master mode.
6 Loop-Back Enable Bit.
Set by user to internally connect the transition to the reception to test user software.
Cleared by user to operate in normal mode.
5 Start Back-Off Disable Bit.
Set by user in multimaster mode. If losing arbitration, the master immediately tries to retransmit.
Cleared by user to enable start back-off. After losing arbitration, the master waits before trying to retransmit.
4
Hardware General Call Enable. When this bit and Bit 3 are set, and have received a general call (Address 0x00) and a data byte, the
device checks the contents of the I2C0ALT against the receive register. If the contents match, the device has received a hardware
general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to.
This is a “to whom it may concern” call. The ADuC7128/ADuC7129 watch for these addresses. The device that requires attention
embeds its own address into the message. All masters listen and the one that can handle the device contacts its slave and acts
appropriately. The LSB of the I2C0ALT register should always be written to a 1, as per the I
2
C January 2000 specification.
3 General Call Enable Bit.
Set this bit to enable the slave device to acknowledge an I
2
C general call, Address 0x00 (write). The device then recognizes a data
bit. If it receives a 0x06 (reset and write programmable part of slave address by hardware) as the data byte, the I
2
C interface resets as per
the I
2
C January 2000 specification. This command can be used to reset an entire I
2
C system. The general call interrupt status bit
sets on any general call. The user must take corrective action by setting up the I
2
C interface after a reset. If it receives a 0x04
(write programmable part of slave address by hardware) as the data byte, the general call interrupt status bit sets on any general
call. The user must take corrective action by reprogramming the device address.
2 Reserved.
1 Master Enable Bit.
Set by user to enable the master I
2
C channel.
Cleared by user to disable the master I
2
C channel.
0 Slave Enable Bit.
Set by user to enable the slave I
2
C channel. A slave transfer sequence is monitored for the device address in I2C0ID0, I2C0ID1,
I2C0ID2, and I2C0ID3. If the device address is recognized, the part participates in the slave transfer sequence.
Cleared by user to disable the slave I
2
C channel.
I2CxDIV Register
Name Address Default Value Access
I2C0DIV 0xFFFF0830 0x1F1F R/W
I2C1DIV 0xFFFF0930 0x1F1F R/W
I2CxDIV are the clock divider registers.
I2CxIDx Register
Name Address Default Value Access
I2C0ID0 0xFFFF0838 0x00 R/W
I2C0ID1 0xFFFF083C 0x00 R/W
I2C0ID2 0xFFFF0840 0x00 R/W
I2C0ID3 0xFFFF0844 0x00 R/W
I2C1ID0 0xFFFF0938 0x00 R/W
I2C1ID1 0xFFFF093C 0x00 R/W
I2C1ID2 0xFFFF0940 0x00 R/W
I2C1ID3 0xFFFF0944 0x00 R/W
I2CxID0, I2CxID1, I2CxID2, and I2CxID3 are slave address
device ID registers of I2Cx.
I2CxSSC Register
Name Address Default Value Access
I2C0SSC 0xFFFF0848 0x01 R/W
I2C1SSC 0xFFFF0948 0x01 R/W
I2CxSSC is an 8-bit start/stop generation counter. It holds off
SDA low for start and stop conditions.