Datasheet

Rev. 0 | Page 67 of 92
I2CxSRX Register
Name Address Default Value Access
I2C0SRX 0xFFFF0808 0x00 R
I2C1SRX 0xFFFF0908 0x00 R
I2CxSRX is a receive register for the slave channel.
I2CxSTX Register
Name Address Default Value Access
I2C0STX 0xFFFF080C 0x00 W
I2C1STX 0xFFFF090C 0x00 W
I2CxSTX is a transmit register for the slave channel.
I2CxMRX Register
Name Address Default Value Access
I2C0MRX 0xFFFF0810 0x00 R
I2C1MRX 0xFFFF0910 0x00 R
I2CxMRX is a receive register for the master channel.
I2CxMTX Register
Name Address Default Value Access
I2C0MTX 0xFFFF0814 0x00 W
I2C1MTX 0xFFFF0914 0x00 W
I2CxMTX is a transmit register for the master channel.
I2CxCNT Register
Name Address Default Value Access
I2C0CNT 0xFFFF0818 0x00 R/W
I2C1CNT 0xFFFF0918 0x00 R/W
I2CxCNT is a master receive data count register. If a master read
transfer sequence is initiated, the I2CxCNT register denotes the
number of bytes (−1) to be read from the slave device. By default
this counter is 0, which corresponds to the expected one byte.
I2CxADR Register
Name Address Default Value Access
I2C0ADR 0xFFFF081C 0x00 R/W
I2C1ADR 0xFFFF091C 0x00 R/W
I2CxADR is a master address byte register. The I2CxADR value
is the device address that the master wants to communicate
with. It is automatically transmitted at the start of a master
transfer sequence if there is no valid data in the I2CxMTX
register when the master enable bit is set.
I2CxBYT Register
Name Address Default Value Access
I2C0BYT 0xFFFF0824 0x00 R/W
I2C1BYT 0xFFFF0924 0x00 R/W
I2CxBYT is a broadcast byte register.
I2CxALT Register
Name Address Default Value Access
I2C0ALT 0xFFFF0828 0x00 R/W
I2C1ALT 0xFFFF0928 0x00 R/W
I2CxALT is a hardware general call ID register used in slave mode.
I2CxCFG Register
Name Address Default Value Access
I2C0CFG 0xFFFF082C 0x00 R/W
I2C1CFG 0xFFFF092C 0x00 R/W
I2CxCFG is a configuration register.
Table 94. I2C0CFG MMR Bit Designations
Bit Description
31:15 Reserved. These bits should be written by the user as 0.
14 Enable Stop Interrupt.
Set by user to generate an interrupt upon receiving a stop condition and after receiving a valid start condition and matching
address.
Cleared by user to disable the generation of an interrupt upon receiving a stop condition.
13 Reserved. This bit should be written by the user as 0.
12 Reserved. This bit should be written by the user as 0.
11 Enable Stretch SCL. Holds SCL low.
Set by user to stretch the SCL line.
Cleared by user to disable stretching of the SCL line.
10 Reserved. This bit should be written by the user as 0.
9 Slave Tx FIFO Request Interrupt Enable.
Cleared by user to generate an interrupt request just after the negative edge of the clock for the R/W bit. This allows the user to
input data into the slave Tx FIFO if it is empty. At 400 kSPS, and with the core clock running at 41.78 MHz, the user has 45 clock
cycles to take appropriate action, taking interrupt latency into account.
Set by user to disable the slave Tx FIFO request interrupt.
8 General Call Status Bit Clear.
Set by user to clear the general call status bits.
Cleared automatically by hardware after the general call status bits have been cleared.