Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 66 of 92
I2CxSSTA Register
Name Address Default Value Access
I2C0SSTA 0xFFFF0804 0x01 R
I2C1SSTA 0xFFFF0904 0x01 R
I2CxSSTA is a status register for the slave channel.
Table 93. I2CxSSTA MMR Bit Designations
Bit Value Description
31:15 Reserved. These bits should be written as 0.
14 START Decode Bit.
Set by hardware if the device receives a valid start and matching address.
Cleared by an I
2
C stop condition or an I
2
C general call reset.
13 Repeated START Decode Bit.
Set by hardware if the device receives a valid repeated start and matching address.
Cleared by an I
2
C stop condition, a read of the I2CxSSTA register, or an I
2
C general call reset.
12:11 ID Decode Bits.
00 Received Address Matched ID Register 0.
01 Received Address Matched ID Register 1.
10 Received Address Matched ID Register 2.
11 Received Address Matched ID Register 3.
10 Stop After Start And Matching Address Interrupt.
Set by hardware if the slave device receives an I
2
C STOP condition after a previous I
2
C START condition
and matching address.
Cleared by a read of the I2CxSSTA register.
9:8 General Call ID.
00 No General Call.
01 General Call Reset and Program Address.
10 General Call Program Address.
11 General Call Matching Alternative ID.
7 General Call Interrupt.
Set if the slave device receives a general call of any type.
Cleared by setting Bit 8 of the I2CxCFG register. If it is a general call reset, all registers are at their default
values. If it is a hardware general call, the Rx FIFO holds the second byte of the general call. This is similar
to the I2C0ALT register (unless it is a general call to reprogram the device address). For more details, see
the I
2
C Bus Specification, Version 2.1, Jan. 2000.
6 Slave Busy.
Set automatically if the slave is busy.
Cleared automatically.
5 No Acknowledge.
Set if master asks for data and no data is available.
Cleared automatically by reading the I2C0SSTA register.
4 Slave Receive FIFO Overflow.
Set automatically if the slave receive FIFO is overflowing.
Cleared automatically by reading I2C0SRX register.
3 Slave Receive IRQ.
Set after receiving data.
Cleared automatically by reading the I2C0SRX register or flushing the FIFO.
2 Slave Transmit IRQ.
Set at the end of a transmission.
Cleared automatically by writing to the I2C0STX register.
1 Slave Transmit FIFO Underflow.
Set automatically if the slave transmit FIFO is underflowing.
Cleared automatically by writing to the I2C0STX register.
0 Slave Transmit FIFO Empty.
Set automatically if the slave transmit FIFO is empty.
Cleared automatically by writing twice to the I2C0STX register.