Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 6 of 92
Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS
3
All logic inputs, including XCLKI and XCLKO
V
INL
, Input Low Voltage 0.8 V
V
INH
, Input High Voltage 2.0 V
Quadrature Encoder Inputs
S1/S2/CLR (Schmitt-Triggered Inputs)
V
T+
1.65 V
V
T−
1.2 V
V
T+
− V
T−
0.75 V
LOGIC OUTPUTS
9
V
OH
, Output High Voltage IOV
DD
−
400 mV
V I
SOURCE
= 1.6 mA
V
OL
, Output Low Voltage 0.4 V I
SINK
= 1.6 mA
CRYSTAL INPUTS XCLKI and XCLKO
V
INL
, Input Low Voltage 1.1 V Logic inputs, XCLKI only
V
INH
, Input High Voltage 1.7 V Logic inputs, XCLKI only
XCLKI, Input Capacitance 20 pF
XCLKO, Output Capacitance 20 pF
MCU CLOCK RATE (PLL)
Eight programmable core clock selections
within this range
326.4 kHz (32.768 kHz x 1275)/128
41.77920 MHz (32.768 kHz x 1275)/1
INTERNAL OSCILLATOR 32.768 kHz
Tolerance ±3 % −40°C to 85°C
±4 % 85°C to 125°C only
STARTUP TIME Core clock = 41.78 MHz
At Power-On 70 ms
From Sleep Mode 1.6 ms
From Stop Mode 1.6 ms
PROGRAMMABLE LOGIC ARRAY (PLA)
Pin Propagation Delay 12 ns From input pin to output pin
Element Propagation Delay 2.5 ns
POWER REQUIREMENTS
Power Supply Voltage Range
IOV
DD
, AV
DD
, and DACV
DD
(Supply
Voltage to Chip)
3.0 3.6 V
LV
DD
(Regulator Output from Chip) 2.5 2.6 2.7 V
Power Supply Current
10, 11
Normal Mode 15 19 mA 5.22 MHz clock
42 49 mA 41.78 MHz clock
Additional Line Driver Tx Supply
Current
30 mA 691 kHz, maximum load (see
Figure 2)
Pause Mode 37 mA 41.78 MHz clock
Sleep Mode 0.3 3.6 mA External crystal or internal OSC ON
1
All ADC channel specifications are guaranteed during normal MicroConverter core operation.
2
Apply to all ADC input channels.
3
Not production tested; supported by design and/or characterization of data on production release.
4
Measured using an external AD845 op amp as an input buffer stage, as shown in Figure 42. Based on external ADC system components.
5
The input signal can be centered on any dc common-mode voltage (V
CM
), as long as this value is within the ADC voltage input range specified.
6
When using an external reference input pin, the internal reference must be disabled by setting the LSB in the REFCON memory mapped register to 0.
7
Endurance is qualified as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +85°C.
8
Retention lifetime equivalent at junction temperature (T
J
) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.
9
Test carried out with a maximum of eight I/Os set to a low output level.
10
Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode = 3.6 V supply, pause mode = 3.6 V
supply, sleep mode = 3.6 V supply.
11
IOV
DD
power supply current decreases typically by 2 mA during a Flash/EE erase cycle.