Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 59 of 92
Table 80. COMxCON0 MMR Bit Designations
Bit Value Name Description
7 DLAB Divisor Latch Access.
Set by user to enable access to COMxDIV0 and COMxDIV1 registers.
Cleared by user to disable access to COMxDIV0 and COMxDIV1 and enable access to COMxRX and COMxTX.
6 BRK Set Break.
Set by user to force SOUT to 0.
Cleared to operate in normal mode.
5 SP Stick Parity.
Set by user to force parity to defined values.
1 if EPS = 1 and PEN = 1
0 if EPS = 0 and PEN = 1
4 EPS Even Parity Select Bit.
Set for even parity.
Cleared for odd parity.
3 PEN Parity Enable Bit.
Set by user to transmit and check the parity bit.
Cleared by user for no parity transmission or checking.
2 STOP Stop Bit.
Set by user to transmit 1.5 stop bits if the word length is 5 bits or 2 stop bits if the word length is 6 bits, 7 bits, or
8 bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected.
Cleared by user to generate 1 stop bit in the transmitted data.
1:0 WLS Word Length Select.
00 5 bits.
01 6 bits.
10 7 bits.
11 8 bits.
Table 81. COMxSTA0 MMR Bit Designations
Bit Name Description
7 RSVD Reserved.
6 TEMT COMxTX Empty Status Bit.
Set automatically if COMxTX is empty.
Cleared automatically when writing to COMxTX.
5 THRE COMxTX and COMxRX Empty.
Set automatically if COMxTX and COMxRX are empty.
Cleared automatically when one of the registers receives data.
4 BI Break Error.
Set when SIN is held low for more than the maximum word length.
Cleared automatically.
3 FE Framing Error.
Set when stop bit invalid.
Cleared automatically.
2 PE Parity Error.
Set when a parity error occurs.
Cleared automatically.
1 OE Overrun Error.
Set automatically if data is overwritten before it is read.
Cleared automatically.
0 DR Data Ready.
Set automatically when COMxRX is full.
Cleared by reading COMxRX.