Datasheet
ADuC7128/ADuC7129
Rev. 0 | Page 58 of 92
Table 77. UART Signal Descriptions
Pin Signal Description
SPM0 (Mode 1) SIN0 Serial Receive Data.
SPM1 (Mode 1) SOUT0 Serial Transmit Data.
SPM2 (Mode 1) RTS0 Request to Send.
SPM3 (Mode 1) CTS0 Clear to Send.
SPM4 (Mode 1) RI0 Ring Indicator.
SPM5 (Mode 1) DCD0 Data Carrier Detect.
SPM6 (Mode 1) DSR0 Data Set Ready.
SPM7 (Mode 1) DTR0 Data Terminal Ready.
SPM8 (Mode 2) SIN0 Serial Receive Data.
SPM9 (Mode 2) SOUT0 Serial Transmit Data.
The serial communication adopts an asynchronous protocol
that supports various word-length, stop-bits, and parity
generation options selectable in the configuration register.
Baud Rate Generation
There are two ways of generating the UART baud rate: normal
450 UART baud rate generation and using the fractional divider.
Normal 450 UART Baud Rate Generation
The baud rate is a divided version of the core clock, using the
value in COM0DIV0 and COM0DIV1 MMRs (16-bit value, DL).
DL
RateBaud
CD
×××
=
2162
MHz78.41
Table 78 gives some common baud rate values.
Table 78. Baud Rate Using the Normal Baud Rate Generator
Baud Rate CD DL Actual Baud Rate % Error
9600 0 0x88 9600 0%
19,200 0 0x44 19,200 0%
115,200 0 0x0B 118,691 3%
9600 3 0x11 9600 0%
19,200 3 0x08 20,400 6.25%
115,200 3 0x01 163,200 41.67%
Using the Fractional Divider
The fractional divider combined with the normal baud rate
generator allows the generating of a wider range of more
accurate baud rates.
/16DL UART
FBEN
CORE
C
LOCK
/2
/(M + N/2048)
0
6020-048
Figure 53. Baud Rate Generation Options
Calculation of the baud rate using fractional divider is as
follows:
)
2048
(2162
MHz78.41
N
MDL
RateBaud
CD
+××××
=
2162
MHz78.41
2048 ××××
=+
DLRateBaud
N
M
CD
For example, generation of 19,200 bauds with CD bits = 3.
Table 78 gives DL = 0x08.
2816219200
MHz78.41
2048
3
××××
=+
N
M
06.1
2048
=+
N
M
where:
M = 1
N = 0.06 × 2048 = 128
( )
2048
128
28162
MHz78.41
3
××××
=RateBaud
where:
Baud Rate = 19,200 bps.
Error = 0% compared to 6.25% with the normal baud rate
generator.
UART Register Definitions
The UART interface consists of 12 registers.
Table 79. UART MMRs
Register Description
COMxTX 8-Bit Transmit Register.
COMxRX 8-Bit Receive Register.
COMxDIV0 Divisor Latch (Low Byte).
COMxTX, COMxRX,
and COMxDIV0
Share The Same Address Location.
COMxTX and COMxRX can be
accessed when Bit 7 in COMxCON0
register is cleared. COMxDIV0 can
be accessed when Bit 7 of
COMxCON0 is set.
COMxDIV1 Divisor Latch (High Byte).
COMxCON0 Line Control Register.
COMxSTA0 Line Status Register.
COMxIEN0 Interrupt Enable Register.
COMxIID0 Interrupt Identification Register.
COMxCON1 Modem Control Register.
COMxSTA1 Modem Status Register.
COMxDIV2 16-Bit Fractional Baud Divide Register.
COMxSCR 8-Bit Scratch Register Used for
Temporary Storage. Also used in
network addressable UART mode.