Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 57 of 92
GPxDAT Register
Name Address Default Value Access
GP0DAT 0xFFFF0D20 0x000000XX R/W
GP1DAT 0xFFFF0D30 0x000000XX R/W
GP2DAT 0xFFFF0D40 0x000000XX R/W
GP3DAT 0xFFFF0D50 0x000000XX R/W
GP4DAT 0xFFFF0D60 0x000000XX R/W
GPxDAT is a Port x configuration and data register. It configures
the direction of the GPIO pins of Port x, sets the output value
for the pins configured as output, and receives and stores the
input value of the pins configured as input.
Table 73. GPxDAT MMR Bit Designations
Bit Description
31:24
Direction of the Data.
Set to 1 by user to configure the GPIO pins as outputs.
Cleared to 0 by user to configure the GPIO pins as
inputs.
23:16 Port x Data Output.
15:8 Reflect the state of Port x pins at reset (read only).
7:0 Port x Data Input (Read Only).
GPxSET Register
Name Address Default Value Access
GP0SET 0xFFFF0D24 0x000000XX W
GP1SET 0xFFFF0D34 0x000000XX W
GP2SET 0xFFFF0D44 0x000000XX W
GP3SET 0xFFFF0D54 0x000000XX W
GP4SET 0xFFFF0D64 0x000000XX W
GPxSET is a data set Port x register.
Table 74. GPxSET MMR Bit Designations
Bit Description
31:24 Reserved.
23:16
Data Port x Set Bit.
Set to 1 by user to set bit on Port x; also sets the
corresponding bit in the GPxDAT MMR.
Cleared to 0 by user; does not affect the data out.
15:0 Reserved.
GPxCLR Register
Name Address Default Value Access
GP0CLR 0xFFFF0D28 0x000000XX W
GP1CLR 0xFFFF0D38 0x000000XX W
GP2CLR 0xFFFF0D48 0x000000XX W
GP3CLR 0xFFFF0D58 0x000000XX W
GP4CLR 0xFFFF0D68 0x000000XX W
GPxCLR is a data clear Port x register.
Table 75. GPxCLR MMR Bit Designations
Bit Description
31:24 Reserved.
23:16
Data Port x Clear Bit.
Set to 1 by user to clear bit on Port x; also clears
the corresponding bit in the GPxDAT MMR.
Cleared to 0 by user; does not affect the data out.
15:0 Reserved.
SERIAL PORT MUX
The serial port mux multiplexes the serial port peripherals (two
I
2
Cs, an SPI, and two UARTs) and the programmable logic array
(PLA) to a set of 10 GPIO pins. Each pin must be configured to
its specific I/O function as described in
Table 76.
Table 76. SPM Configuration
Pin
GPIO
(00)
UART
(01)
UART/I2C/SPI
(10)
PLA
(11)
SPM0 P1.0 SIN0 I2C0SCL PLAI[0]
SPM1 P1.1 SOUT0 I2C0SDA PLAI[1]
SPM2 P1.2 RTS0 I2C1SCL PLAI[2]
SPM3 P1.3 CTS0 I2C1SDA PLAI[3]
SPM4 P1.4 RI0 SPICLK PLAI[4]
SPM5 P1.5 DCD0 SPIMISO PLAI[5]
SPM6 P1.6 DSR0 SPIMOSI PLAI[6]
SPM7 P1.7 DTR0 SPICSL PLAO[0]
SPM8 P0.7 ECLK SIN0 PLAO[4]
SPM9 P2.0
1
PWMSYNC SOUT0 PLAO[5]
SPM10 P2.2
1
RTS1 RS PLAO[7]
SPM11 P2.3
1
CTS1 AE
SPM12 P2.4
1
RI1 MS0
SPM13 P2.5
1
DCD1 MS1
SPM14 P2.6
1
DSR1 MS2
SPM15 P2.7
1
DTR1 MS3
SPM16 P4.6 SIN1 AD14 PLAO[14]
SPM17 P4.7 SOUT1 AD15 PLAO[15]
1
Available only on the 80-lead ADuC7129.
Table 76 details the mode for each of the SPMUX GPIO pins.
This configuration has to be performed via the GP0CON,
GP1CON and GP2CON MMRs. By default these pins are
configured as GPIOs.
UART SERIAL INTERFACE
The ADuC7128/ADuC7129 contain two identical UART
blocks. Although only UART0 is described here, UART1
functions in exactly the same way.
The UART peripheral is a full-duplex universal asynchronous
receiver/transmitter, fully compatible with the 16450 serial port
standard.
The UART performs serial-to-parallel conversion on data
characters received from a peripheral device or a modem, and
parallel-to-serial conversion on data characters received from
the CPU. The UART includes a fractional divider for baud rate
generation and has a network-addressable mode. The UART
function is made available on 10 pins of the ADuC7128/
ADuC7129 (see
Table 77).