Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 56 of 92
Table 70. GPIO Pin Function Designations
Configuration
Port Pin 00 01 10 11
0 P0.0 GPIO CMP MS0 PLAI[7]
P0.1
1
GPIO BLE -
P0.2
1
GPIO BHE
P0.3 GPIO
TRST
A16 ADC
B
BUSY
B
P0.4 GPIO/IRQ0
CONVST
MS1 PLAO[1]
P0.5 GPIO/IRQ1 ADC
BUSY
PLM_COMP PLAO[2]
P0.6 GPIO/T1
MRST
AE PLAO[3]
P0.7 GPIO ECLK/XCLK
2
P
SIN0 PLAO[4]
1 P1.0 GPIO/T1 SIN0 SCL0 PLAI[0]
P1.1 GPIO SOUT0 SDA0 PLAI[1]
P1.2 GPIO RTS0 SCL1 PLAI[2]
P1.3 GPIO CTS0 SDA1 PLAI[3]
P1.4 GPIO/IRQ2 RI0 CLK PLAI[4]
P1.5 GPIO/IRQ3 DCD0 MISO PLAI[5]
P1.6 GPIO DSR0 MOSI PLAI[6]
P1.7 GPIO DTR0 CSL PLAO[0]
2 P2.0 GPIO SYNC SOUT PLAO[5]
P2.1
1
GPIO WS PLAO[6]
P2.2
1
GPIO RTS1 RS PLAO[7]
P2.3
1
GPIO CTS1 AE
P2.4
1
GPIO RI1 MS0
P2.5
1
GPIO DCD1 MS1
P2.6
1
GPIO DSR1 MS2
P2.7
1
GPIO DTR1 MS3
3 P3.0 GPIO PWM1 AD0 PLAI[8]
P3.1 GPIO PWM2 AD1 PLAI[9]
P3.2 GPIO PWM3 AD2 PLAI[10]
P3.3 GPIO PWM4 AD3 PLAI[11]
P3.4 GPIO PWM5 AD4 PLAI[12]
P3.5 GPIO PWM6 AD5 PLAI[13]
P3.6
1
GPIO PWM1 AD6 PLAI[14]
P3.7
1
GPIO PWM3 AD7 PLAI[15]
4 P4.0 GPIO QENS1 AD8 PLAO[8]
P4.1 GPIO QENS2 AD9 PLAO[9]
P4.2 GPIO RSVD AD10 PLAO[10]
P4.3 GPIO
Trip
(Shutdown)
AD11 PLAO[11]
P4.4 GPIO PLMIN AD12 PLAO[12]
P4.5 GPIO PLMOUT AD13 PLAO[13]
P4.6 GPIO SIN1 AD14 PLAO[14]
P4.7 GPIO SOUT1 AD15 PLAO[15]
1
Available only on the 80-lead ADuC7129.
2
When configured in Mode 1, PO.7 is ECLK by default, or core clock output. To
configure it as a clock ouput, the MDCLK bits in PLLCON must be set to 11.
Table 71. GPxCON MMR Bit Designations
Bit Description
31:30 Reserved
29:28 Select function of Px.7 pin
27:26 Reserved
25:24 Select function of Px.6 pin
23:22 Reserved
21:20 Select function of Px.5 pin
19:18 Reserved
17:16 Select function of Px.4 pin
15:14 Reserved
13:12 Select function of Px.3 pin
11:10 Reserved
9:8 Select function of Px.2 pin
7:6 Reserved
5:4 Select function of Px.1 pin
3:2 Reserved
1:0 Select function of Px.0 pin
GPxPAR Register
Name Address Default Value Access
GP0PAR 0xFFFF0D2C 0x20000000 R/W
GP1PAR 0xFFFF0D3C 0x00000000 R/W
GP3PAR 0xFFFF0D5C 0x00222222 R/W
GP4PAR 0xFFFF0D6C 0x00000000 R/W
GPxPAR programs the parameters for Port 0, Port 1, Port 3, and
Port 4. Note that the GPxDAT MMR must always be written
after changing the GPxPAR MMR.
Table 72. GPxPAR MMR Bit Designations
Bit Description
31:29 Reserved
28 Pull-up disable Px.7 pin
27:25 Reserved
24 Pull-up disable Px.6 pin
23:21 Reserved
20 Pull-up disable Px.5 pin
19:17 Reserved
16 Pull-up disable Px.4 pin
15:13 Reserved
12 Pull-up disable Px.3 pin
11:9 Reserved
8 Pull-up disable Px.2 pin
7:5 Reserved
4 Pull-up disable Px.1 pin
3:1 Reserved
0 Pull-up disable Px.0 pin