Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 53 of 92
Table 67. PWMCON2 MMR Bit Designations
Bit Value Name Description
7 CSEN
Set to 1 by the user to enable the PWM
to generate a convert start signal.
Cleared by user to disable the PWM
convert start signal.
6:4 RSVD
Reserved. This bit should be set to 0 by
the user.
CSD3
Convert Start Delay. Delays the convert
start signal by a number of clock pulses.
CSD2
CSD1
CSD0
0000 4 clock pulses.
0001 8 clock pulses.
0010 12 clock pulses.
0011 16 clock pulses.
0100 20 clock pulses.
0101 24 clock pulses.
0110 28 clock pulses.
0111 32 clock pulses.
1000 36 clock pulses.
1001 40 clock pulses.
1010 44 clock pulses.
1011 48 clock pulses.
1100 52 clock pulses.
1101 56 clock pulses.
1110 60 clock pulses.
3:0
1111 64 clock pulses.
When calculating the time from the convert start delay to the
start of an ADC conversion, the user needs to take account of
internal delays. The example below shows the case for a delay of
four clocks. One additional clock is required to pass the convert
start signal to the ADC logic. Once the ADC logic receives the
convert start signal an ADC conversion begins on the next
ADC clock edge (see
Figure 50).
UCLOCK
LOW SIDE
COUNT
PWM SIGNAL
S
IGNAL PASSED
TO ADC LOGIC
06020-045
TO CONVST
Figure 50. ADC Conversion
Quadrature Encoder
A quadrature encoder is used to determine both the speed and
direction of a rotating shaft. In its most common form, there are
two digital outputs, S1 and S2. As the shaft rotates, both S1 and
S2 toggle; however, they are 90° out of phase. The leading output
determines the direction of rotation. The time between each
transition indicates the speed of rotation.
CLOCKWISE COUNTER CLOCKWISE
S1 S2
00
01
11
10
00
01
11
10
00
01
11
10
00
06020-046
Figure 51. Quadrate Encoder Input Values
The quadrature encoder takes the incremental input shown in
Figure 51 and increments or decrements a counter depending
on the direction and speed of the rotating shaft.
On the ADuC7128/ADuC7129, the internal counter is clocked
on the rising edge of the S1 input, and the S2 input indicates the
direction of rotation/count. The counter increments when S2
is high and decrements when it is low.
In addition, if the software has prior knowledge of the direction
of rotation, one input can be ignored (S2) and the other can act
as a clock (S1).
For additional flexibility, all inputs can be internally inverted
prior to use.
The quadrature encoder operates asynchronously from the
system clock.
Input Filtering
Filtering can be applied to the S1 input by setting the FILTEN
bit in QENCON. S1 normally acts as the clock to the counter;
however, the filter can be used to ignore positive edges on S1
unless there has been a high or a low pulse on S2 between two
positive edges on S1 (see
Figure 52).
S1
S2 HIGH PULSE
S2 LOW PULSE
06020-047
Figure 52. S1 Input Filtering