Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 52 of 92
Bit Name Description
2.
4.
8.
16.
32.
64.
128.
6 PWMCP0
256.
5 POINV Set to 1 by the user to invert all PWM outputs.
Cleared by user to use PWM outputs as normal.
4 HOFF High Side Off.
Set to 1 by the user to force PWM1 and PWM3 outputs high. This also forces PWM2 and PWM4 low.
Cleared by user to use the PWM outputs as normal.
3 LCOMP Load Compare Registers.
Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of the
PWM timer from 0x00 to 0x01.
Cleared by user to use the values previously stored in the internal compare registers.
2 DIR Direction Control.
Set to 1 by the user to enable PWM1 and PWM2 as the output signals while PWM3 and PWM4 are held low.
Cleared by user to enable PWM3 and PWM4 as the output signals while PWM1 and PWM2 are held low.
1 HMODE Enables H-bridge mode.
Set to 1 by the user to enable H-Bridge mode and Bit 1 to Bit 5 of PWMCON1.
Cleared by user to operate the PWMs in standard mode.
0 PWMEN Set to 1 by the user to enable all PWM outputs.
Cleared by user to disable all PWM outputs.
In H-bridge mode, HMODE = 1. See Table 65 to determine the PWM outputs.
Table 65. PWM Output Selection
PWMCOM1 MMR PWM Outputs
ENA HOFF POINV DIR PWM1 PWM2 PWMR3 PWM4
0 0 x x 1 1 1 1
x 1 x x 1 0 1 0
1 0 0 0 0 0 HS
1
LS
1
1 0 0 1 HS
1
LS
1
0 0
1 0 1 0 HS
1
LS
1
1 1
1 0 1 1 1 1 HS
1
LS
1
1
HS = high side, LS = low side.
On power-up, PWMCON1 defaults to 0x12 (HOFF = 1 and
HMODE = 1). All GPIO pins associated with the PWM are
configured in PWM mode by default (see
Table 66).
Table 66. Compare Register
Name Address Default Value Access
PWM1COM1 0xFFFF0F84 0x00 R/W
PWM1COM2 0xFFFF0F88 0x00 R/W
PWM1COM3 0xFFFF0F8C 0x00 R/W
PWM2COM1 0xFFFF0F94 0x00 R/W
PWM2COM2 0xFFFF0F98 0x00 R/W
PWM2COM3 0xFFFF0F9C 0x00 R/W
PWM3COM1 0xFFFF0FA4 0x00 R/W
PWM3COM2 0xFFFF0FA8 0x00 R/W
PWM3COM3 0xFFFF0FAC 0x00 R/W
The PWM trip interrupt can be cleared by writing any value to
the PWMICLR MMR. Note that when using the PWM trip
interrupt, the PWM interrupt should be cleared before exiting
the ISR. This prevents generation of multiple interrupts.
PWM CONVERT START CONTROL
The PWM can be configured to generate an ADC convert start
signal after the active low side signal goes high. There is a program-
mable delay between when the low-side signal goes high and
the convert start signal is generated.
This is controlled via the PWMCON2 MMR. If the delay
selected is higher than the width of the PWM pulse, the
interrupt remains low.