Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 51 of 92
DIGITAL PERIPHERALS
PWM GENERAL OVERVIEW
The ADuC7128/ADuC7129 integrate a six channel PWM inter-
face. The PWM outputs can be configured to drive an H-bridge
or can be used as standard PWM outputs. On power up, the PWM
outputs default to H-bridge mode. This ensures that the motor
is turned off by default. In standard PWM mode, the outputs
are arranged as three pairs of PWM pins. Users have control
over the period of each pair of outputs and over the duty cycle
of each individual output.
Table 63. PWM MMRs
Name Description
PWMCON1 PWM Control
PWM1COM1 Compare Register 1 for PWM Outputs 1 and 2
PWM1COM2 Compare Register 2 for PWM Outputs 1 and 2
PWM1COM3 Compare Register 3 for PWM Outputs 1 and 2
PWM1LEN Frequency Control for PWM Outputs 1 and 2
PWM2COM1 Compare Register 1 for PWM Outputs 3 and 4
PWM2COM2 Compare Register 2 for PWM Outputs 3 and 4
PWM2COM3 Compare Register 3 for PWM Outputs 3 and 4
PWM2LEN Frequency Control for PWM Outputs 3 and 4
PWM3COM1 Compare Register 1 for PWM Outputs 5 and 6
PWM3COM2 Compare Register 2 for PWM Outputs 5 and 6
PWM3COM3 Compare Register 3 for PWM Outputs 5 and 6
PWM3LEN Frequency Control for PWM Outputs 5 and 6
PWMCON2 PWM Convert Start Control
PWMICLR PWM Interrupt Clear
In all modes, the PWMxCOMx MMRs controls the point at
which the PWM outputs change state. An example of the first pair
of PWM outputs (PWM1 and PWM2) is shown in
Figure 49.
HIGH SIDE
(PWM1)
LOW SIDE
(PWM2)
PWM1COM3
PWM1COM2
PWM1COM1
PWM1LEN
0
6020-044
Figure 49. PWM Timing
The PWM clock is selectable via PWMCON1 with one of the
following values: UCLK/2, 4, 8, 16, 32, 64, 128, or 256. The
length of a PWM period is defined by PWMxLEN.
The PWM waveforms are set by the count value of the 16-bit
timer and the compare registers contents as shown with the
PWM1 and PWM2 waveforms above.
The low-side waveform, PWM2, goes high when the timer
count reaches PWM1LEN, and it goes low when the timer
count reaches the value held in PWM1COM3 or when the
high-side waveform PWM1 goes low.
The high-side waveform, PWM1, goes high when the timer
count reaches the value held in PWM1COM1, and it goes low
when the timer count reaches the value held in PWM1COM2.
Table 64. PWMCON1 MMR Bit Designations
Bit Name Description
14 SYNC Enables PWM Synchronization.
Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low
transition on the SYNC pin.
Cleared by user to ignore transitions on the SYNC pin.
13 PWM6INV Set to 1 by the user to invert PWM6.
Cleared by user to use PWM6 in normal mode.
12 PWM4NV Set to 1 by the user to invert PWM4.
Cleared by user to use PWM4 in normal mode.
11 PWM2INV Set to 1 by the user to invert PWM2.
Cleared by user to use PWM2 in normal mode.
10 PWMTRIP
Set to 1 by the user to enable PWM trip interrupt. When the PWMTRIP input is low, the PWMEN bit is cleared and an
interrupt is generated.
Cleared by user to disable the PWMTRIP interrupt.
9 ENA If HOFF = 0 and HMODE = 1.
Set to 1 by the user to enable PWM outputs.
Cleared by user to disable PWM outputs.
If HOFF = 1 and HMODE = 1, see
Table 65.
If not in H-Bridge mode, this bit has no effect.
8 PWMCP2 PWM Clock Prescaler Bits.
7 PWMCP1 Sets UCLK divider.