Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 48 of 92
Comparator Interface
The comparator interface consists of a 16-bit MMR, CMPCON, described in Table 57.
Table 57. CMPCON MMR Bit Designations
Bit Value Name Description
15:11 Reserved.
10 CMPEN Comparator Enable Bit.
Set by user to enable the comparator.
Cleared by user to disable the comparator.
Note: A comparator interrupt is generated on the enable of the comparator. This should be cleared in the
user software.
Comparator Negative Input Select Bits.
00 AVDD/2.
01 ADC3 input.
10 V
REF
× 0.6.
9:8
11
CMPIN
Reserved.
Comparator Output Configuration Bits.
00 IRQ and PLA connections disabled.
01 IRQ and PLA connections disabled.
10 PLA connections enabled.
7:6
11
CMPOC
IRQ connections enabled.
5 CMPOL Comparator Output Logic State Bit.
When low, the comparator output is high when the positive input (CMP0) is above the negative
input (CMP1).
When high, the comparator output is high when the positive input is below the negative input.
Response Time.
00
5 s response time typical for large signals (2.5 V differential).
17 s response time typical for small signals (0.65 mV differential).
01 Reserved.
10 Reserved.
4:3
11
CMPRES
3 s response time typical for any signal type.
2 CMPHYST Comparator Hysteresis Bit.
Set by user to have a hysteresis of about 7.5 mV.
Cleared by user to have no hysteresis.
1 CMPORI Comparator Output Rising Edge Interrupt.
Set automatically when a rising edge occurs on the monitored voltage (CMP0).
Cleared by user by writing a 1 to this bit.
0 CMPOFI Comparator Output Falling Edge Interrupt.
Set automatically when a falling edge occurs on the monitored voltage (CMP0).
Cleared by user.