Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 42 of 92
Table 41. FEExSTA MMR Bit Designations
Bit Description
15:6 Reserved.
5 Reserved.
4 Reserved.
3 Flash/EE Interrupt Status Bit.
Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the
FEExMOD register is set.
Cleared when reading FEExSTA register.
2 Flash/EE Controller Busy.
Set automatically when the controller is busy.
Cleared automatically when the controller is not busy.
1 Command Fail.
Set automatically when a command completes unsuccessfully.
Cleared automatically when reading FEExSTA register.
0 Command Complete.
Set by MicroConverter when a command is complete.
Cleared automatically when reading FEExSTA register.
Table 42. FEExMOD MMR Bit Designations
Bit Description
7:5 Reserved.
4 Flash/EE Interrupt Enable.
Set by user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete.
Cleared by user to disable the Flash/EE interrupt
3 Erase/Write Command Protection.
Set by user to enable the erase and write commands.
Cleared to protect the Flash/EE memory against erase/write command.
2 Reserved. Should always be set to 0 by the user.
1:0 Flash/EE Wait States. Both Flash/EE blocks must have the same wait state value for any change to take effect.
Table 43. Command Codes in FEExCON
Code Command Description
0x00
1
Null Idle State.
0x01
1
Single read Load FEExDAT with the 16-bit data indexed by FEExADR.
0x02
1
Single write Write FEExDAT at the address pointed by FEExADR. This operation takes 50 µs.
0x03
1
Erase/Write
Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation
takes 20 ms.
0x04
1
Single verify
Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison
is returned in FEExSTA Bit 1.
0x05
1
Single erase Erase the page indexed by FEExADR.
0x06
1
Mass erase
Erase user space. The 2 kB of kernel are protected in Block 0. This operation takes 2.48 sec. To prevent accidental
execution, a command sequence is required to execute this instruction.
0x07 Reserved Reserved.
0x08 Reserved Reserved.
0x09 Reserved Reserved.
0x0A Reserved Reserved.
0x0B Signature Gives a signature of the 64 kB of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32,778 clock cycles.
0x0C Protect
This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase
(0x06) or with the key.
0x0D Reserved Reserved.
0x0E Reserved Reserved.
0x0F Ping No Operation, Interrupt Generated.
1
The FEExCON register always reads 0x07 immediately after execution of any of these commands.