Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 32 of 92
ADC CIRCUIT OVERVIEW
The analog-to-digital converter (ADC) incorporates a fast,
multichannel, 12-bit ADC. It can operate from 3.0 V to 3.6 V
supplies and is capable of providing a throughput of up to 1 MSPS
when the clock source is 41.78 MHz. This block provides the
user with a multichannel multiplexer, differential track-and-
hold, on-chip reference, and ADC.
The ADC consists of a 12-bit successive approximation converter
based around two capacitor DACs. Depending on the input
signal configuration, the ADC can operate in one of the
following three modes:
• Fully differential mode, for small and balanced signals
• Single-ended mode, for any single-ended signals
• Pseudo differential mode, for any single-ended signals,
taking advantage of the common mode rejection offered by
the pseudo differential input
The converter accepts an analog input range of 0 to V
REF
when
operating in single-ended mode or pseudo differential mode. In
fully differential mode, the input signal must be balanced around
a common-mode voltage V
CM
, in the range 0 V to AV
DD
and
with a maximum amplitude of 2 V
REF
(see Figure 32).
AV
DD
V
CM
V
CM
V
CM
0
2V
REF
2V
REF
2V
REF
0
6020-028
Figure 32. Examples of Balanced Signals for Fully Differential Mode
A high precision, low drift, and factory-calibrated 2.5 V reference
is provided on-chip. An external reference can also be connected
as described in the
Band Gap Reference section.
Single or continuous conversion modes can be initiated in software.
An external
CONVST
pin, an output generated from the on-chip
PLA, a Timer0, or a Timer1 overflow can also be used to
generate a repetitive trigger for ADC conversions.
If the signal has not been deasserted by the time the ADC
conversion is complete, a second conversion begins auto-
matically.
A voltage output from an on-chip band gap reference propor-
tional to absolute temperature can also be routed through the
front-end ADC multiplexer, effectively an additional ADC
channel input. This facilitates an internal temperature sensor
channel, measuring die temperature to an accuracy of ±3°C.
ADC TRANSFER FUNCTION
Pseudo Differential Mode and Single-Ended Mode
In pseudo differential or single-ended mode, the input range is
0 to V
REF
. The output coding is straight binary in pseudo
differential and single-ended modes with
1 LSB = FS/4096 or
2.5 V/4096 = 0.61 mV or
610 µV when V
REF
= 2.5 V
The ideal code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …,
FS – 3/2 LSBs). The ideal input/output transfer characteristic is
shown in
Figure 33.
OUTPUT CODE
VOLTAGE INPUT
1111 1111 1111
1111 1111 1110
1111 1111 1101
1111 1111 1100
0000 0000 0011
1LSB0V +FS – 1LSB
0000 0000 0010
0000 0000 0001
0000 0000 0000
1LSB =
FS
4096
06020-029
Figure 33. ADC Transfer Function in Pseudo Differential Mode or
Single-Ended Mode
Fully Differential Mode
The amplitude of the differential signal is the difference
between the signals applied to the V
IN+
and V
IN−
pins (that is,
V
IN+
− V
IN−
). The maximum amplitude of the differential signal
is, therefore, −V
REF
to +V
REF
p-p (2 × V
REF
). This is regardless of
the common mode (CM). The common mode is the average of
the two signals (V
IN+
+ V
IN−
)/2, and is, therefore, the voltage upon
which the two inputs are centered. This results in the span of
each input being CM ± V
REF
/2. This voltage has to be set up exter-
nally, and its range varies with V
REF
(see the Driving the Analog
Inputs
section).
The output coding is twos complement in fully differential
mode with 1 LSB = 2 V
REF
/4096 or 2 × 2.5 V/4096 = 1.22 mV
when V
REF
= 2.5 V. The output result is ±11 bits, but this is
shifted by one to the right. This allows the result in ADCDAT to
be declared as a signed integer when writing C code. The
designed code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …,
FS − 3/2 LSBs). The ideal input/output transfer characteristic is
shown in
Figure 34.