Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 31 of 92
Table 30. QEN Base Address = 0xFFFF0F00
Address Name Byte Access Type Cycle
0x0F00 QENCON 2 R/W 2
0x0F04 QENSTA 1 R 2
0x0F08 QENDAT 2 R/W 2
0x0F0C QENVAL 2 R 2
0x0F14 QENCLR 1 W 2
0x0F18 QENSET 1 W 2
Table 31. PWM Base Address = 0xFFFF0F80
Address Name Byte Access Type Cycle
0x0F80
PWMCON1
2 R/W 2
0x0F84
PWM1COM1
2 R/W 2
0x0F88
PWM1COM2
2 R/W 2
0x0F8C
PWM1COM3
2 R/W 2
0x0F90
PWM1LEN
2 R/W 2
0x0F94
PWM2COM1
2 R/W 2
0x0F98
PWM2COM2
2 R/W 2
0x0F9C
PWM2COM3
2 R/W 2
0x0FA0
PWM2LEN
2 R/W 2
0x0FA4
PWM3COM1
2 R/W 2
0x0FA8
PWM3COM2
2 R/W 2
0x0FAC
PWM3COM3
2 R/W 2
0x0FB0
PWM3LEN
2 R/W 2
0x0FB4
PWMCON2
2 R/W 2
0x0FB8
PWMICLR
2 W 2