Datasheet

ManualsBrandsANALOG DEVICES ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 80 (12x12) 16/32-Bit 41.78 MHz I/O number 38

ADuC7128/ADuC7129

Rev. 0 | Page 28 of 92

SPI

0xFFFF0900

0xFFFF0848

0xFFFF0800

0xFFFF076C

0xFFFF0740

0xFFFF0948

0xFFFF0B00

0xFFFF0A00

0xFFFF0A14

UART0

0xFFFF072C

0xFFFF0700

UART1

FLASH CONTROL

INTERFACE 0

0xFFFFFFF

0xFFFF0B54

0xFFFF0C00

0xFFFF0C30

EXTERNAL MEMORY

PLA

0xFFFF0D00

0xFFFF0D70

GPIO

0xFFFF0E00

0xFFFF0E28

FLASH CONTROL

INTERFACE 1

0xFFFF0E80

0xFFFF0EA8

QEN

0xFFFF0F00

0xFFFF0F18

PWM

0xFFFF0F80

0xFFFF0FBC

INTERRUPT

CONTROLLER

REMAP AND

SYSTEM CONTROL

DDS

DAC

ADC

BANDGAP

REFERENCE

POWER SUPPLY

MONITOR

TIMER 0

GENERAL PURPOSE

TIMER 4

WATCHDOG

TIMER

GENERAL PURPOSE

TIMER

WAKEUP

TIMER

0xFFFF0000

0xFFFF0110

0xFFFF0320

0xFFFF0318

0xFFFF0300

0xFFFF0240

0xFFFF0200

0xFFFF0670

xFFFF06BC

0xFFFF0690

0xFFFF0688

0xFFFF0500

0xFFFF0544

0xFFFF04A8

0xFFFF0480

0xFFFF0334

0xFFFF0448

0xFFFF0440

0xFFFF0434

0xFFFF0400

0xFFFF0340

0xFFFF0350

0xFFFF0360

0xFFFF0370

PLL AND

OSCILLATOR

CONTROL

0xFFFF0380

0xFFFF0394

6020-027

Figure 31. Memory Mapped Registers

COMPLETE MMR LISTING

Note that the Access Type column corresponds to the access

time reading or writing an MMR. It depends on the AMBA bus

used to access the peripheral. The processor has two AMBA

buses: the AHB (advanced high performance bus) used for

system modules and the APB (advanced peripheral bus) used

for lower performance peripherals.

Table 12. IRQ Base Address = 0xFFFF0000

Address Name Byte Access Type Cycle

0x0000 IRQSTA 4 R 1

0x0004 IRQSIG 4 R 1

0x0008 IRQEN 4 R/W 1

0x000C IRQCLR 4 W 1

0x0010 SWICFG 4 W 1

0x0100 FIQSTA 4 R 1

0x0104 FIQSIG 4 R 1

0x0108 FIQEN 4 R/W 1

0x010C FIQCLR 4 W 1

Table 13. System Control Base Address = 0xFFFF0200

Address Name Byte Access Type Cycle

0x0220 REMAP 1 R/W 1

0x0230 RSTSTA 1 R 1

0x0234 RSTCLR 1 W 1

Table 14. Timer Base Address = 0xFFFF0300

Address Name Byte Access Type Cycle

0x0300 T0LD 2 R/W 2

0x0304 T0VAL0 2 R 2

0x0308 T0VAL1 4 R 2

0x030C T0CON 4 R/W 2

0x0310 T0ICLR 1 W 2

0x0314 T0CAP 2 R 2

0x0320 T1LD 4 R/W 2

0x0324 T1VAL 4 R 2

0x0328 T1CON 4 R/W 2

0x032C T1ICLR 1 W 2

0x0330 T1CAP 4 R 2

0x0340 T2LD 4 R/W 2

0x0344 T2VAL 4 R 2

0x0348 T2CON 4 R/W 2

0x034C T2ICLR 1 W 2

0x0360 T3LD 2 R/W 2

0x0364 T3VAL 2 R 2

0x0368 T3CON 2 R/W 2

0x036C T3ICLR 1 W 2

0x0380 T4LD 4 R/W 2

0x0384 T4VAL 4 R 2

0x0388 T4CON 4 R/W 2

0x038C T4ICLR 1 W 2

0x0390 T4CAP 4 R 2

Table 15. PLL Base Address = 0xFFFF0400

Address Name Byte Access Type Cycle

0x0404 POWKEY1 2 W 2

0x0408 POWCON 2 R/W 2

0x040C POWKEY2 2 W 2

0x0410 PLLKEY1 2 W 2

0x0414 PLLCON 2 R/W 2

0x0418 PLLKEY2 2 W 2

Table 16. PSM Base Address = 0xFFFF0440

Address Name Byte Access Type Cycle

0x0440 PSMCON 2 R/W 2

0x0444 CMPCON 2 R/W 2

Table 17. Reference Base Address = 0xFFFF0480

Address Name Byte Access Type Cycle

0x048C REFCON 1 R/W 2