Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 26 of 92
USABLE IN USER MODE
SYSTEM MODES ONLY
SPSR_UND
SPSR_IRQ
SPSR_ABT
SPSR_SVC
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R13_UND
R14_UND
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15 (PC)
R13_IRQ
R14_IRQ
R13_ABT
R14_ABT
R13_SVC
R14_SVC
SPSR_FIQ
CPSR
USER MODE
FIQ
MODE
SVC
MODE
ABORT
MODE
IRQ
MODE
UNDEFINED
MODE
0
6020-024
Figure 28. Register Organization
INTERRUPT LATENCY
The worst case latency for an FIQ consists of the following:
• The longest time the request can take to pass through the
synchronizer
• The time for the longest instruction to complete (the
longest instruction is an LDM) that loads all the registers,
including the PC
• The time for the data abort entry
• The time for FIQ entry
At the end of this time, the ARM7TDMI executes the instruction
at Address 0x1C (FIQ interrupt vector address). The maximum
total time is 50 processor cycles, which is just under 1.2 µs in a
system using a continuous 41.78 MHz processor clock.
The maximum IRQ latency calculation is similar, but it must
allow for the fact that FIQ has higher priority and could delay
entry into the IRQ handling routine for an arbitrary length of
time. This time can be reduced to 42 cycles if the LDM command
is not used; some compilers have an option to compile without
using this command. Another option is to run the part in Thumb
mode, where the time is reduced to 22 cycles.
The minimum latency for FIQ or IRQ interrupts is five cycles.
It consists of the shortest time the request can take through the
synchronizer plus the time to enter the exception mode.
Note that the ARM7TDMI always runs in ARM (32-bit) mode
when in privileged modes, that is, when executing interrupt
service routines.