Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 16 of 92
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TCK
TDO
IOGND
IOV
DD
LV
DD
DGND
P3.0/PWM1 P3.1/PWM2 P3.2/PWM3 P3.3/PWM4
P0.3/AD
C
BUSY
/TRST
RST
P3.4/PWM5 P3.5/PWM6
P0.4/IRQ0/CONVST
P0.5/IRQ1/ADC
BUSY
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ADC4 ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 DACV
DD
AV
DD
AGND DACGND V
REF
P4.5 P4.4 P4.3/PWM
TRIP
P4.2 P1.0/SPM0 P1.1/SPM1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ADC5
VDAC
OUT
ADC9
ADC10
GND
REF
ADCNEG
AV
DD
ADC12/LD1TX
ADC13/LD2TX
AGND
TMS
TDI
P4.6/SPM10
P4.7/SPM11
P0.0/BM/CMP
OUT
P0.6/T1/MRST
P1.2/SPM2
P1.3/SPM3
P1.4/SPM4
P1.5/SPM5
P4.1/S2
P4.0/S1
IOV
DD
IOGND
P1.6/SPM6
P1.7/SPM7
DGND
PV
DD
XCLKI
XCLKO
P0.7/SPM8/ECLK/XCLK
P2.0/SPM9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
ADuC7128
TOP VIEW
(Not to Scale)
0
6020-063
Figure 10. ADuC7128 Pin Configuration
Table 10. ADuC7128 Pin Function Descriptions
Pin
No.
Mnemonic Type
1
Description
1 ADC5 I Single-Ended or Differential Analog Input 5/Line Driver Input.
2 VDAC
OUT
O Output from DAC Buffer.
3 ADC9 I Single-Ended or Differential Analog Input 9.
4 ADC10 I Single-Ended or Differential Analog Input 10.
5 GND
REF
S
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
6 ADCNEG I
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be
connected to the ground of the signal to convert. This bias point must be between
0 V and 1 V.
7, 58 AV
DD
S Analog Power.
8 ADC12/LD1TX I/O Single-Ended or Differential Analog Input 12/DAC Differential Negative Output.
9 ADC13/LD2TX I/O Single-Ended or Differential Analog Input 13/DAC Differential Positive Output.
10, 57 AGND S Analog Ground. Ground reference point for the analog circuitry.
11 TMS I JTAG Test Port Input, Test Mode Select. Debug and download access.
12 TDI I JTAG Test Port Input, Test Data In. Debug and download access.
13 P4.6/SPM10 I/O General-Purpose Input and Output Port 4.6/Serial Port Mux Pin 10.
14 P4.7/SPM11 I/O General-Purpose Input and Output Port 4.7/Serial Port Mux Pin 11.
15
P0.0/
BM/CMP
OUT
I/O
General-Purpose Input and Output Port 0.0/Boot Mode. The ADuC7128 enters download
mode if
BM is low at reset and executes code if BM is pulled high at reset through a 1 kΩ
resistor/voltage comparator output.
16
P0.6/T1/
MRST
O General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output.
17 TCK I JTAG Test Port Input, Test Clock. Debug and download access.
18 TDO O JTAG Test Port Output, Test Data Out. Debug and download access.
19, 41 IOGND S Ground for GPIO. Typically connected to DGND.
20, 42 IOV
DD
S 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.