Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 12 of 92
Table 6. SPI Master Mode Timing (PHASE Mode = 0)
Parameter Description Min Typ Max Unit
t
SL
SCLOCK low pulse width
1
(SPIDIV + 1) × t
HCLK
ns
t
SH
SCLOCK high pulse width
1
(SPIDIV + 1) × t
HCLK
ns
t
DAV
Data output valid after SCLOCK edge 2 × t
HCLK
+ 2 × t
UCLK
ns
t
DOSU
Data output setup before SCLOCK edge 75 ns
t
DSU
Data input setup time before SCLOCK edge
2
1 × t
UCLK
ns
t
DHD
Data input hold time after SCLOCK edge
2
2 × t
UCLK
ns
t
DF
Data output fall time 5 12.5 ns
t
DR
Data output rise time 5 12.5 ns
t
SR
SCLOCK rise time 5 12.5 ns
t
SF
SCLOCK fall time 5 12.5 ns
1
t
HCLK
depends on the clock divider or CD bits in the PLLCON MMR, t
HCLK
= t
UCLK
/2
CD
.
2
t
UCLK
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SCLOCK
(POLARITY = 0)
SCLOCK
(POLARITY = 1)
t
SH
t
SL
t
SR
t
SF
MOSI MSB BIT 6 TO BIT 1 LSB
MISO MSB IN BIT 6 TO BIT 1 LSB IN
t
DR
t
DF
t
DAV
t
DOSU
t
DSU
t
DHD
06020-005
Figure 7. SPI Master Mode Timing (PHASE Mode = 0)