Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 10 of 92
I
2
C® Timing Specifications
Table 4. IP
2
P
C Timing in Fast Mode (400 kHz)
Parameter Description Slave Min Slave Max Master Typ Unit
t
L
SCLOCK low pulse width
1
200 1360 ns
t
H
SCLOCK high pulse width
1
100 1140 ns
t
SHD
Start condition hold time 300 251,350 ns
t
DSU
Data setup time 100 740 ns
t
DHD
Data hold time 0 400 ns
t
RSU
Setup time for repeated start 100 12.51350 ns
t
PSU
Stop condition setup time 100 400 ns
t
BUF
Bus-free time between a stop condition and a start condition 1.3 μs
t
R
Rise time for both SCLOCK and SDATA 100 300 200 ns
t
F
Fall time for both SCLOCK and SDATA 60 300 20 ns
t
SUP
Pulse width of spike suppressed 50 ns
1
t
HCLK
depends on the clock divider or CD bits in the PLLCON MMR, t
HCLK
= t
UCLK
/2
CD
.
S
DATA (I/O)
t
BUF
MSB LSB ACK MSB
1982–71
SCLOCK (I)
PS
STOP
CONDITION
START
CONDITION
S(R)
REPEATED
START
t
SUP
t
R
t
F
t
F
t
R
t
H
t
L
t
SUP
t
DSU
t
DHD
t
RSU
t
DHD
t
DSU
t
SHD
t
PSU
0
6020-003
Figure 5. I
P
2
P
C-Compatible Interface Timing