Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 98 of 108
XMCFG Register
Name: XMCFG
Address: 0xFFFFF000
Default Value: 0x00
Access: Read/write
XMCFG is set to 1 to enable external memory access. This must
be set to 1 before any port pins can function as external memory
access pins. The port pins must also be individually enabled via
the GPxCON MMR.
Table 148. XMxCON Registers
Name Address Default Value Access
XM0CON 0xFFFFF010 0x00 R/W
XM1CON 0xFFFFF014 0x00 R/W
XM2CON 0xFFFFF018 0x00 R/W
XM3CON 0xFFFFF01C 0x00 R/W
XMxCON are the control registers for each memory region.
They allow the enabling/disabling of a memory region and
control the data bus width of the memory region.
Table 149. XMxCON MMR Bit Descriptions
Bit Description
1 Selects data bus width.
Set by the user to select a 16-bit data bus.
Cleared by the user to select an 8-bit data bus.
0 Enables memory region.
Set by the user to enable memory region.
Cleared by the user to disable the memory region.
Table 150. XMxPAR Registers
Name Address Default Value Access
XM0PAR 0xFFFFF020 0x70FF R/W
XM1PAR 0xFFFFF024 0x70FF R/W
XM2PAR 0xFFFFF028 0x70FF R/W
XM3PAR 0xFFFFF02C 0x70FF R/W
XMxPAR are registers that define the protocol used for
accessing the external memory for each memory region.
Table 151. XMxPAR MMR Bit Descriptions
Bit Description
15
Enable byte write strobe. This bit is only used for two
8-bit memory blocks sharing the same memory region.
Set by the user to gate the A0 output with the WS
output. This allows byte write capability without using
BHE
and BLE signals.
Cleared by user to use BHE
and BLE signals.
[14:12] Number of wait states on the address latch enable strobe.
11 Reserved.
10 Extra address hold time.
Set by the user to disable extra hold time.
Cleared by the user to enable one clock cycle of hold
on the address in read and write.
9 Extra bus transition time on read.
Set by the user to disable extra bus transition time.
Cleared by the user to enable one extra clock before
and after the read strobe (RS
).
8 Extra bus transition time on write.
Set by the user to disable extra bus transition time.
Cleared by the user to enable one extra clock before and
after the write strobe (WS
).
[7:4] Number of write wait states.
Select the number of wait states added to the length of
the WS
pulse. 0x0 is 1 clock; 0xF is 16 clock cycles (default
value).
[3:0] Number of read wait states.
Select the number of wait states added to the length of
the RS
pulse. 0x0 is 1 clock; 0xF is 16 clock cycles
(default value).
Figure 58, Figure 59, Figure 60, and Figure 61 show the timing
for a read cycle, a read cycle with address hold and bus turn
cycles, a write cycle with address and write hold cycles, and a
write cycle with wait sates, respectively.