Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 94 of 108
Table 142. T1CON MMR Bit Descriptions
Bit Value Description
[31:18] Reserved.
17 Event select bit.
Set by user to enable time capture of an event.
Cleared by the user to disable time capture of an
event.
[16:12]
Event select range, 0 to 25. These events are as
described in Table 126. All events are offset by
two, that is, Event 2 in Table 126 becomes Event
0 for the purposes of Timer0.
[11:9] Clock select.
000 Core clock (41 MHz/2
CD
).
001 32.768 kHz.
010 UCLK.
011 P1.0 raising edge triggered.
8 Count up.
Set by the user for Timer1 to count up.
Cleared by the user for Timer1 to count down
by default.
7 Timer1 enable bit.
Set by the user to enable Timer1.
Cleared by the user to disable Timer1 by default.
6 Timer1 mode.
Set by the user to operate in periodic mode.
Cleared by the user to operate in free-running
mode. Default mode.
[5:4] Format.
00 Binary.
01 Reserved.
10 Hr: min: sec: hundredths (23 hours to 0 hour).
11 Hr: min: sec: hundredths (255 hours to 0 hour).
[3:0] Prescale.
0000 Source clock/1.
0100 Source clock/16.
1000 Source clock/256.
1111 Source clock/32,768.
T1CLRI Register
Name: T1CLRI
Address: 0xFFFF032C
Default Value: 0xFF
Access: Write only
T1CLRI is an 8-bit register. Writing any value to this register
clears the Timer1 interrupt.
T1CAP Register
Name: T1CAP
Address: 0xFFFF0330
Default Value: 0x00000000
Access: Read/write
T1CAP is a 32-bit register. It holds the value contained in
T1VAL when a particular event occurrs. This event must be
selected in T1CON.
Timer2 (Wake-Up Timer)
Timer2 is a 32-bit wake-up timer, count down or count up, with
a programmable prescaler. The prescaler is clocked directly from
one of four clock sources, including the core clock (default selec-
tion), the internal 32.768 kHz oscillator, the external 32.768 kHz
watch crystal, or the PLL undivided clock. The selected clock
source can be scaled by a factor of 1, 16, 256, or 32,768. The
wake-up timer continues to run when the core clock is disabled.
This gives a minimum resolution of 22 ns when the core is
operating at 41.78 MHz and with a prescaler of 1. Capture of
the current timer value is enabled if the Timer2 interrupt is
enabled via IRQEN[4] (see Table 126).
The counter can be formatted as a plain 32-bit value or as
hours: minutes: seconds: hundredths.
Timer2 reloads the value from T2LD either when Timer2
overflows or immediately when T2CLRI is written.
The Timer2 interface consists of four MMRs, shown in
Table 143.
Table 143. Timer2 Interface Registers
Register Description
T2LD 32-bit register. Holds 32-bit unsigned integers.
T2VAL
32-bit register. Holds 32-bit unsigned integers. This
register is read only.
T2CLRI
8-bit register. Writing any value to this register clears
the Timer2 interrupt.
T2CON Configuration MMR.
Timer2 Load Registers
Name: T2LD
Address: 0xFFFF0340
Default Value: 0x00000
Access: Read/write
T2LD is a 32-bit register, which holds the 32-bit value that is
loaded into the counter.
Timer2 Clear Register
Name: T2CLRI
Address: 0xFFFF034C
Default Value: 0x00
Access: Write only
This 8-bit write-only MMR is written (with any value) by user
code to refresh (reload) Timer2.