Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 88 of 108
IRQP2 Register
Name: IRQP2
Address: 0xFFFF0028
Default Value: 0x00000000
Access: Read/write
Table 132. IRQP2 MMR Bit Descriptions
Bit Name Description
31 Reserved.
[30:28] IRQ3PI A priority level of 0 to 7 can be set for IRQ3.
27 Reserved.
[26:24] IRQ2PI A priority level of 0 to 7 can be set for IRQ2.
23 Reserved.
[22:20] PLA0PI
A priority level of 0 to 7 can be set for PLA
IRQ0.
19 Reserved.
[18:16] IRQ1PI A priority level of 0 to 7 can be set for IRQ1.
15 Reserved.
[14:12] PSMPI
A priority level of 0 to 7 can be set for the
power supply monitor interrupt source.
11 Reserved.
[10:8] COMPI
A priority level of 0 to 7 can be set for the
comparator.
7 Reserved.
[6:4] IRQ0PI A priority level of 0 to 7 can be set for IRQ0.
3 Reserved.
[2:0] SPIPI A priority level of 0 to 7 can be set for SPI.
IRQP3 Register
Name: IRQP3
Address: 0xFFFF002C
Default Value: 0x00000000
Access: Read/write
Table 133. IRQP3 MMR Bit Descriptions
Bit Name Description
[31:7] Reserved.
[6:4] PWMPI A priority level of 0 to 7 can be set for PWM.
3 Reserved.
[2:0] PLA1PI
A priority level of 0 to 7 can be set for PLA
IRQ1.
IRQCONN Register
The IRQCONN register is the IRQ and FIQ control register. It
contains two active bits: the first to enable nesting and prioritiza-
tion of IRQ interrupts and the other to enable nesting and
prioritization of FIQ interrupts.
If these bits are cleared, FIQs and IRQs can still be used, but it is
not possible to nest IRQs or FIQs, nor is it possible to set an
interrupt source priority level. In this default state, an FIQ does
have a higher priority than an IRQ.
Name: IRQCONN
Address: 0xFFFF0030
Default Value: 0x00000000
Access: Read/write
Table 134. IRQCONN MMR Bit Descriptions
Bit Name Description
31:2
Reserved. These bits are reserved and should
not be written to.
1 ENFIQN
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
0 ENIRQN
Setting this bit to 1 enables nesting of IRQ
interrupts. Clearing this bit means no nesting
or prioritization of IRQs is allowed.
IRQSTAN Register
If IRQCONN Bit 0 is asserted and IRQVEC is read, one of the
IRQSTAN[7:0] bits is asserted. The bit that asserts depends on
the priority of the IRQ. If the IRQ is of Priority 0, then Bit 0
asserts, if Priority 1, then Bit 1 asserts, and so on. When a bit is
set in this register, all interrupts of that priority and lower are
blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit at a time. For
example, if this register is set to 0x09, writing 0xFF changes the
register to 0x08, and writing 0xFF a second time changes the
register to 0x00.
Name: IRQSTAN
Address: 0xFFFF003C
Default Value: 0x00000000
Access: Read/write
Table 135. IRQSTAN MMR Bit Descriptions
Bit Name Description
31:8
Reserved. These bits are reserved and should
not be written to.
7:0
Setting these bits to 1 enables nesting of FIQ
interrupts. Clearing these bits means no
nesting or prioritization of FIQs is allowed.