Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 83 of 108
PLAADC Register
Name: PLAADC
Address: 0xFFFF0B48
Default Value: 0x00000000
Access: Read/write
PLAADC is the PLA source for the ADC start conversion signal.
Table 123. PLAADC MMR Bit Descriptions
Bit Value Description
[31:5] Reserved.
4 ADC start conversion enable bit.
Set by the user to enable ADC start
conversion from PLA.
Cleared by the user to disable ADC start
conversion from PLA.
[3:0] ADC start conversion source.
0000 PLA Element 0.
0001 PLA Element 1.
1111 PLA Element 15.
PLADIN Register
Name: PLADIN
Address: 0xFFFF0B4C
Default Value: 0x00000000
Access: Read/write
PLADIN is a data input MMR for PLA.
Table 124. PLADIN MMR Bit Descriptions
Bit Description
[31:16] Reserved.
[15:0] Input bit to Element 15 to Element 0.
PLADOUT Register
Name: PLADOUT
Address: 0xFFFF0B50
Default Value: 0x00000000
Access: Read only
PLADOUT is a data output MMR for PLA. This register is
always updated.
Table 125. PLADOUT MMR Bit Descriptions
Bit Description
[31:16] Reserved.
[15:0] Output bit from Element 15 to Element 0.
PLALCK Register
Name: PLALCK
Address: 0xFFFF0B54
Default Value: 0x00
Access: Write only
PLALCK is a PLA lock option. Bit 0 is written only once. When
set, it does not allow modification of any of the PLA MMRs,
except PLADIN. A PLA tool is provided in the development
system to easily configure the PLA.