Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 8 of 108
Parameter Min Typ Max Unit Test Conditions/Comments
ESD TESTS 2.5 V reference, T
A
= 25°C
HBM Passed Up To 3 kV
FICDM Passed Up To 1.5 kV
1
All ADC channel specifications are guaranteed during normal core operation.
2
Apply to all ADC input channels.
3
Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).
4
Not production tested but supported by design and/or characterization data on production release.
5
Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 37. Based on external ADC
system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).
6
The input signal can be centered on any dc common-mode voltage (V
CM
) as long as this value is within the ADC voltage input range specified.
7
DAC linearity is calculated using a reduced code range of 100 to 3995.
8
DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V V
REF
.
9
Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
10
Retention lifetime equivalent at junction temperature (T
J
) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.
11
Test carried out with a maximum of eight I/Os set to a low output level.
12
Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with
3.6 V supply, and sleep mode with 3.6 V supply.
13
IOV
DD
power supply current increases typically by 2 mA during a Flash/EE erase cycle.
14
This current must be added to the AV
DD
current.
TIMING SPECIFICATIONS
I
2
C Timing
Table 2. I
2
C Timing in Fast Mode (400 kHz)
Slave Master
Parameter Description Min Max Typ Unit
t
L
SCL low pulse width 200 1360 ns
t
H
SCL high pulse width 100 1140 ns
t
SHD
Start condition hold time 300 ns
t
DSU
Data setup time 100 740 ns
t
DHD
Data hold time 0 400 ns
t
RSU
Setup time for repeated start 100 ns
t
PSU
Stop condition setup time 100 800 ns
t
BUF
Bus-free time between a stop condition and a start condition 1.3 µs
t
R
Rise time for both SCL and SDA 300 200 ns
t
F
Fall time for both SCL and SDA 300 ns
Table 3. I
2
C Timing in Standard Mode (100 kHz)
Slave
Parameter Description Min Max Unit
t
L
SCL low pulse width 4.7 µs
t
H
SCL high pulse width 4.0 ns
t
SHD
Start condition hold time 4.0 µs
t
DSU
Data setup time 250 ns
t
DHD
Data hold time 0 3.45 µs
t
RSU
Setup time for repeated start 4.7 µs
t
PSU
Stop condition setup time 4.0 µs
t
BUF
Bus-free time between a stop condition and a start condition 4.7 µs
t
R
Rise time for both SCL and SDA 1 µs
t
F
Fall time for both SCL and SDA 300 ns