Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 71 of 108
Master Mode
In master mode, the I2CxADR0 register is programmed with
the I
2
C address of the device.
In 7-bit address mode, I2CxADR0[7:1] are set to the device
address. I2CxADR0[0] is the read/write bit.
In 10-bit address mode, the 10-bit address is created as follows:
I2CxADR0[7:3] must be set to 11110b.
I2CxADR0[2:1] = Address Bits[9:8].
I2CxADR1[7:0] = Address Bits[7:0].
I2CxADR0[0] is the read/write bit.
I
2
C Registers
The I
2
C peripheral interfaces consists of a number of MMRs.
These are described in the I2C Master Registers section.
I
2
C Master Registers
I
2
C Master Control Register
Name: I2C0MCON, I2C1MCON
Address: 0xFFFF0800, 0xFFFF0900
Default
Va lu e :
0x0000, 0x0000
Access: Read/write
Function: This 16-bit MMR configures the I
2
C peripheral in
master mode.
Table 102. I2CxMCON MMR Bit Descriptions
Bit Name Description
[15:9] Reserved. These bits are reserved and should not be written to.
8 I2CMCENI I
2
C transmission complete interrupt enable bit.
Set this bit to enable an interrupt on detecting a stop condition on the I
2
C bus.
Clear this bit to clear the interrupt source.
7 I2CNACKENI I
2
C no acknowledge (NACK) received interrupt enable bit.
Set this bit to enable interrupts when the I
2
C master receives a NACK.
Clear this bit to clear the interrupt source.
6 I2CALENI I
2
C arbitration lost interrupt enable bit.
Set this bit to enable interrupts when the I
2
C master is unable to gain control of the I
2
C bus.
Clear this bit to clear the interrupt source.
5 I2CMTENI I
2
C transmit interrupt enable bit.
Set this bit to enable interrupts when the I
2
C master has transmitted a byte.
Clear this bit to clear the interrupt source.
4 I2CMRENI I
2
C receive interrupt enable bit.
Set this bit to enable interrupts when the I
2
C master receives data.
Cleared by user to disable interrupts when the I
2
C master is receiving data.
I2CMSEN I
2
C master SCL stretch enable bit.
Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until
I2CMSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.
3
Clear this bit to disable clock stretching.
2 I2CILEN I
2
C internal loopback enable.
Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their
respective input signals.
Cleared by the user to disable loopback mode.
1 I2CBD I
2
C master backoff disable bit.
Set this bit to allow the device to compete for control of the bus even if another device is currently driving a start
condition.
Clear this bit to wait until the I
2
C bus becomes free.
0 I2CMEN I
2
C master enable bit.
Set by the user to enable I
2
C master mode.
Clear this bit to disable I
2
C master mode.