Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 68 of 108
SPIRX Register
Name: SPIRX
Address: 0xFFFF0A04
Default Value: 0x00
Access: Read only
Function: This 8-bit MMR is the SPI receive register.
SPITX Register
Name: SPITX
Address: 0xFFFF0A08
Default Value: 0x00
Access: Write only
Function: This 8-bit MMR is the SPI transmit register.
SPIDIV Register
Name: SPIDIV
Address: 0xFFFF0A0C
Default Value: 0x00
Access: Read/write
Function: This 8-bit MMR is the SPI baud rate selection
register.
SPICON Register
Name: SPICON
Address: 0xFFFF0A10
Default Value: 0x0000
Access: Read/write
Function: This 16-bit MMR configures the SPI
peripheral in both master and slave modes.
Table 101. SPICON MMR Bit Descriptions
Bit Name Description
[15:14] SPIMDE SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer.
[00] = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have
been received into the FIFO.
[01] = Tx interrupt occurs when two bytes have been transferred. Rx interrupt occurs when two or more bytes have
been received into the FIFO.
[10] = Tx interrupt occurs when three bytes have been transferred. Rx interrupt occurs when three or more bytes
have been received into the FIFO.
[11] = Tx interrupt occurs when four bytes have been transferred. Rx interrupt occurs when the Rx FIFO is full or four
bytes are present.
13 SPITFLH SPI Tx FIFO flush enable bit.
Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required.
If this bit is left high, then either the last transmitted value or 0x00 is transmitted, depending on the SPIZEN bit.
Any writes to the Tx FIFO are ignored while this bit is set.
Clear this bit to disable Tx FIFO flushing.
12 SPIRFLH SPI Rx FIFO flush enable bit.
Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required.
If this bit is set incoming, data is ignored and no interrupts are generated.
If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer.
Clear this bit to disable Rx FIFO flushing.
Continuous transfer enable.
Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available
in the SPITX register. CS
is asserted and remains asserted for the duration of each 8-bit serial transfer until SPITX is
empty.
11 SPICONT
Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer.
If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle.
10 SPILP Loopback enable bit.
Set by the user to connect MISO to MOSI and test software.
Cleared by the user to be in normal mode.