Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 60 of 108
The drive strength bits can be written only once after reset.
Additional writing to related bits has no effect on drive strength.
The GPIO drive strength and pull-up disable are not always
adjustable for GPIO port. Some control bits cannot be changed.
See Table 78 for details.
Table 84. GPxDAT Registers
Name Address Default Value Access
GP0DAT 0xFFFFF420 0x000000XX R/W
GP1DAT 0xFFFFF430 0x000000XX R/W
GP2DAT 0xFFFFF440 0x000000XX R/W
GP3DAT 0xFFFFF450 0x000000XX R/W
GP4DAT 0xFFFFF460 0x000000XX R/W
The GPxDAT are Port x configuration and data registers. They
configure the direction of the GPIO pins of Port x, set the
output value for the pins configured as output, and store the
input value of the pins configured as input.
Table 85. GPxDAT MMR Bit Descriptions
Bit Description
[31:24] Direction of the data.
Set to 1 by the user to configure the GPIO pin as
an output.
Cleared to 0 by the user to configure the GPIO pin
as an input.
[23:16] Port x data output.
[15:8] Reflect the state of Port x pins at reset (read only).
[7:0] Port x data input (read only).
Table 86. GPxSET Registers
Name Address Default Value Access
GP0SET 0xFFFFF424 0x000000XX W
GP1SET 0xFFFFF434 0x000000XX W
GP2SET 0xFFFFF444 0x000000XX W
GP3SET 0xFFFFF454 0x000000XX W
GP4SET 0xFFFFF464 0x000000XX W
The GPxSET are data set Port x registers.
Table 87. GPxSET MMR Bit Descriptions
Bit Description
[31:24] Reserved.
[23:16] Data Port x set bit.
Set to 1 by the user to set a bit on Port x; also sets the
corresponding bit in the GPxDAT MMR.
Cleared to 0 by the user; does not affect the data output.
[15:0] Reserved.
Table 88. GPxCLR Registers
Name Address Default Value Access
GP0CLR 0xFFFFF428 0x000000XX W
GP1CLR 0xFFFFF438 0x000000XX W
GP2CLR 0xFFFFF448 0x000000XX W
GP3CLR 0xFFFFF458 0x000000XX W
GP4CLR 0xFFFFF468 0x000000XX W
The GPxCLR are data clear Port x registers.
Table 89. GPxCLR MMR Bit Descriptions
Bit Description
[31:24] Reserved.
[23:16] Data Port x clear bit.
Set to 1 by the user to clear a bit on Port x; also clears
the corresponding bit in the GPxDAT MMR.
Cleared to 0 by the user; does not affect the data out.
[15:0] Reserved.
SERIAL PORT MUX
The serial port mux multiplexes the serial port peripherals
(an SPI, UART, and two I
2
Cs) and the programmable logic array
(PLA) to a set of 10 GPIO pins. Each pin must be configured to
one of its specific I/O functions as described in Table 90.
Table 90. SPM Configuration
GPIO UART UART/I
2
C/SPI PLA
SPM
(00) (01) (10) (11)
SPM0 P1.0 SIN0 I2C0SCL PLAI[0]
SPM1 P1.1 SOUT0 I2C0SDA PLAI[1]
SPM2 P1.2 RTS I2C1SCL PLAI[2]
SPM3 P1.3 CTS I2C1SDA PLAI[3]
SPM4 P1.4 RI SCLK PLAI[4]
SPM5 P1.5 DCD MISO PLAI[5]
SPM6 P1.6 DSR MOSI PLAI[6]
SPM7 P1.7 DTR
CS
PLAO[0]
SPM8 P0.7 ECLK/XCLK SIN0 PLAO[4]
SPM9 P2.0
CONV
START
SOUT0 PLAO[5]
SPM10 P4.0 SIN1 AD8 PLAO[8]
SPM11 P4.1 SOUT1 AD9 PLAO[9]
SPM12 P2.3 N/A AE SIN1
SPM13 P2.4 PWM0 MSO SOUT1
Tabl e 90 also details the mode for each of the SPMMUX pins.
This configuration has to be done via the GP0CON, GP1CON,
and GP2CON MMRs. By default, these 10 pins are configured
as GPIOs.
UART SERIAL INTERFACE
The UART peripheral is a full-duplex, universal, asynchronous
receiver/transmitter. The UART performs serial-to-parallel conver-
sions on data characters received from a peripheral device and
parallel-to-serial conversions on data characters received from
the CPU. The ADuC7124/ADuC7126 has been equipped with
two industry standard 16,450 type UARTs (UART0 and UART1).
Each UART features a fractional divider that facilitates high accu-
racy baud rate generation and is equipped with a 16-byte FIFO
for the transmitter and a 16-byte FIFO for the receiver. Both
UARTs can be configured as FIFO mode and non-FIFO mode.
The serial communication adopts an asynchronous protocol,
which supports various word lengths, stop bits, and parity
generation options selectable in the configuration register.