Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 46 of 108
Table 45. FEE1STA Register
Name Address Default Value Access
FEE1STA 0xFFFFF880 0x0000 R
Table 46. FEE1MOD Register
Name Address Default Value Access
FEE1MOD 0xFFFFF884 0x80 R/W
Table 47. FEE1CON Register
Name Address Default Value Access
FEE1CON 0xFFFFF888 0x00 R/W
Table 48. FEE1DAT Register
Name Address Default Value Access
FEE1DAT 0xFFFFF88C 0xXXXX R/W
FEE1DAT is a 16-bit data register.
Table 49. FEE1ADR Register
Name Address Default Value Access
FEE1ADR 0xFFFFF890 0x0000 R/W
FEE1ADR is a 16-bit address register.
Table 50. FEE1SGN Register
Name Address Default Value Access
FEE1SGN 0xFFFFF898 0xFFFFFF R
FEE1SGN is a 24-bit code signature.
Table 51. FEE1PRO Register
Name Address Default Value Access
FEE1PRO 0xFFFFF89C 0x00000000 R/W
FEE1PRO provides protection following subsequent reset MMR.
It requires a software key (see Table 57).
Table 52. FEE1HID Register
Name Address Default Value Access
FEE1HID 0xFFFFF8A0 0xFFFFFFFF R/W
FEE1HID provides immediate protection MMR. It does not
require any software keys (see Table 57).
Command Sequence for Executing a Mass Erase
FEE0DAT = 0x3CFF;
FEE0ADR = 0xFFC3;
FEE0MOD = FEE0MOD|0x8; //Erase key enable
FEE0CON = 0x06; //Mass erase
command
Table 53. FEExSTA MMR Bit Descriptions
Bit Description
[15:6] Reserved.
5 Reserved.
4 Reserved.
3 Flash/EE interrupt status bit.
Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the
FEExMOD register is set.
Cleared when reading the FEExSTA register.
2 Flash/EE controller busy.
Set automatically when the controller is busy.
Cleared automatically when the controller is not busy.
1 Command fail.
Set automatically when a command completes unsuccessfully.
Cleared automatically when reading the FEExSTA register.
0 Command complete.
Set by MicroConverter when a command is complete.
Cleared automatically when reading the FEExSTA register.