Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 39 of 108
Bit Value Description
[2:0] Conversion type.
000
Enable CONV
START
pin as a conversion input.
001 Enable Timer1 as a conversion input.
010 Enable Timer0 as a conversion input.
011
Single software conversion. Sets to 000 after
conversion (note that Bit 7 of ADCCON MMR
should be cleared after starting a single
software conversion to avoid further
conversions triggered by the CONV
START
pin).
100 Continuous software conversion.
101 PLA conversion.
Other Reserved.
ADCCP Register
Name: ADCCP
Address: 0xFFFF0504
Default Value: 0x00
Access: Read/write
ADCCP is an ADC positive channel selection register. This
MMR is described in Table 31.
Table 31. ADCCP
1
MMR Bit Designation
Bit Value Description
[7:5] Reserved.
[4:0] Positive channel selection bits.
00000 ADC0.
00001 ADC1.
00010 ADC2.
00011 ADC3.
00100 ADC4.
00101 ADC5.
00110 ADC6.
00111 ADC7.
01000 ADC8.
01001 ADC9.
01010 ADC10.
01011 ADC11.
01100 DAC0/ADC12.
01101 DAC1/ADC13.
01110 DAC2/ADC14.
01111 DAC3/ADC15.
10000 Temperature sensor.
10001 AGND (self-diagnostic feature).
10010 Internal reference (self-diagnostic feature).
10011 AV
DD
/2.
Others Reserved.
1
ADC and DAC channel availability depends on part model. See the Ordering
Guide for details.
ADCCN Register
Name: ADCCN
Address: 0xFFFF0508
Default Value: 0x01
Access: Read/write
ADCCN is an ADC negative channel selection register. This
MMR is described in Table 32.
Table 32. ADCCN MMR Bit Designation
Bit Value Description
[7:5] Reserved.
[4:0] Negative channel selection bits.
00000 ADC0.
00001 ADC1.
00010 ADC2.
00011 ADC3.
00100 ADC4.
00101 ADC5.
00110 ADC6.
00111 ADC7.
01000 ADC8.
01001 ADC9.
01010 ADC10.
01011 ADC11.
01100 DAC0/ADC12.
01101 DAC1/ADC13.
01110 DAC2/ADC14.
01111 DAC3/ADC15.
10000 Reserved.
10001 AGND.
10010 Reserved.
10011 Reserved.
Others Reserved.
ADCSTA Register
Name: ADCSTA
Address: 0xFFFF050C
Default Value: 0x00
Access: Read only
ADCSTA is an ADC status register that indicates when an ADC
conversion result is ready. The ADCSTA register contains only
one bit, ADCReady (Bit 0), representing the status of the ADC.
This bit is set at the end of an ADC conversion, generating an
ADC interrupt. It is cleared automatically by reading the
ADCDAT MMR. When the ADC is performing a conversion,
the status of the ADC can be read externally via the ADC
BUSY
pin. This pin is high during a conversion. When the conversion
is finished, ADC
BUSY
goes back low. This information is available