Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 20 of 108
Pin No. Mnemonic Description
34 P3.3/AD3/PWM3/PLAI[11]
General-Purpose Input and Output Port 3.3 (P3.3).
External Memory Interface (AD3).
PWM Phase 3 (PWM3).
Programmable Logic Array Input Element 11 (PLAI[11]).
35 P2.4/SPM13/PWM0/MS0/SOUT1
General-Purpose Input and Output Port 2.4 (P2.4).
Serial Port Multiplexed (SPM13)
PWM Phase 0 (PWM0).
External Memory Select 0 (MS0).
UART1 Output (SOUT1).
36 P0.3/TRST/A16/ADC
BUSY
General-Purpose Input and Output Port 0.3 (P0.3).
JTAG Test Port Input, Test Reset (TRST).JTAG Reset Input. Debug and download access. If
this pin is held low, JTAG access is not possible because the JTAG interface is held in
reset and P0.1/P0.2/P0.3 are configured as GPIO pins.
Address Line (A16).
ADC
BUSY
Signal Output (ADC
BUSY
).
37 P2.5/PWM1/MS1
General-Purpose Input and Output Port 2.5 (P2.5).
PWM Phase 1 (PWM1).
External Memory Select 1 (MS1).
38 P2.6/PWM2/MS2
General-Purpose Input and Output Port 2.6 (P2.6).
PWM Phase 2 (PWM2).
External Memory Select 2 (MS2).
39 P3.4/AD4/PWM4/PLAI[12]
General-Purpose Input and Output Port 3.4 (P3.4).
External Memory Interface (AD4).
PWM Phase 4 (PWM4).
Programmable Logic Array Input 12 (PLAI[12]).
40 P3.5/AD5/PWM5/PLAI[13]
General-Purpose Input and Output Port 3.5 (P3.5).
External Memory Interface (AD5).
PWM Phase 5 (PWM5).
Programmable Logic Array Input Element 13 (PLAI[13]).
41
RST
Reset Input, Active Low.
42 IRQ0/P0.4/PWM
TRIP
/PLAO[1]/MS1
Multifunction I/O Pin.
External Interrupt Request 0, Active High (IRQ0).
General-Purpose Input and Output Port 0.4 (P0.4).
PWM Trip External Input (PWM
TRIP
).
Programmable Logic Array Output Element 1 (PLAO[1]).
External Memory Select 1 (MS1)..
43 IRQ1/P0.5/ADC
BUSY
/PLAO[2]/MS2
Multifunction I/O Pin.
External Interrupt Request 1, Active High (IRQ1).
General-Purpose Input and Output Port 0.5 (P0.5).
ADC
BUSY
Signal Output (ADC
BUSY
).
Programmable Logic Array Output Element 2 (PLAO[2]).
External Memory Select 2 (MS2).
44 P2.7/PWM3/MS3
General-Purpose Input and Output Port 2.7 (P2.7).
PWM Phase 3 (PWM3).
External Memory Select 3 (MS3).
45
P2.0/SPM9/PLAO[5]/
CONV
START
/SOUT0
General-Purpose Input and Output Port 2.0 (P2.0).
Serial Port Multiplexed (SPM9).
Programmable Logic Array Output Element 5 (PLAO[5]).
Start Conversion Input Signal for ADC (
CONV
START
).
UART0 Output (SOUT0).
46 P0.7/SPM8/ECLK/XCLK/PLAO[4]/SIN0
General-Purpose Input and Output Port 0.7 (P0.7).
Serial Port Multiplexed (SPM8).
Output for External Clock Signal (ECLK).
Input to the Internal Clock Generator Circuits (XCLK).
Programmable Logic Array Output Element 4 (PLAO[4]).
UART0 Input (SIN0).
47 IOGND Ground for GPIO. Typically connected to DGND.
48 IOV
DD
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.