Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 19 of 108
Pin No. Mnemonic Description
11 DAC0/ADC12
DAC0 Voltage Output (DAC0).
Single-Ended or Differential Analog Input 12 (ADC12).
12 DAC1/ADC13
DAC1 Voltage Output (DAC1).
Single-Ended or Differential Analog Input 13 (ADC13).
13 DAC2/ADC14
DAC2 Voltage Output (DAC2).
Single-Ended or Differential Analog Input 14 (ADC14).
14 DAC3/ADC15
DAC3 Voltage Output (DAC3).
Single-Ended or Differential Analog Input 15 (ADC15).
15 TMS JTAG Test Port Input, Test Mode Select. Debug and download access.
16 TDI JTAG Test Port Input, Test Data In. Debug and download access.
17
P0.1/PWM4/BLE
General-Purpose Input and Output Port 0.1 (P0.1).
PWM Phase 4 (PWM4).
External Memory Byte Low Enable (BLE).
18 XCLKO Output from the Crystal Oscillator Inverter.
19 XCLKI
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator
Circuits.
20 BM/P0.0/CMP
OUT
/PLAI[7]/MS0
Multifunction I/O Pin.
Boot Mode Entry Pin (BM). The ADuC7126 enters UART download mode if BM is low at
reset and executes code if BM is pulled high at reset through a 1 kΩ resistor.. The
ADuC7126 enters I
2
C download mode in I
2
C version parts if BM is low at reset with a
flash address of 0x800014 = 0xFFFFFFFFF. The ADuC7126 executes code if BM is pulled
high at reset or if BM is low at reset with a flash address 0x800014 ≠ 0xFFFFFFFFF.
General-Purpose Input and Output Port 0.0 (P0.0).
Voltage Comparator Output/Programmable Logic Array Input Element 7 (CMP
OUT
).
External Memory Select 0 (MS0). By default, this pin is configured as GPIO.
21 DGND Ground for Core Logic.
22 LV
DD
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47
µF capacitor to DGND only.
23 IOV
DD
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
24 IOGND Ground for GPIO. Typically connected to DGND.
25 P4.6/AD14/PLAO[14]
General-Purpose Input and Output Port 4.6 (P4.6).
External Memory Interface (AD14).
Programmable Logic Array Output Element 14 (PLAO[14]).
26 P4.7/AD15/PLAO[15]
General-Purpose Input and Output Port 4.7 (P4.7).
External Memory Interface (AD15).
Programmable Logic Array Output Element 15 (PLAO[15]).
27 P0.6/T1/MRST/PLAO[3]/MS3
Multifunction Pin, Driven Low After Reset.
General-Purpose Output Port 0.6 (P0.6).
Timer1 Input (T1).
Power-On Reset Output (MRST).
Programmable Logic Array Output Element 3 (PLAO[3]).
External Memory Select 3 (MS3).
28 TCK JTAG Test Port Input, Test Clock. Debug and download access.
29 TDO JTAG Test Port Output, Test Data Out. Debug and download access.
30
P0.2/PWM5/BHE
General-Purpose Input and Output Port 0.2 (P0.2).
PWM Phase 5 (PWM5).
External Memory Byte High Enable (BHE).
31 P3.0/AD0/PWM0/PLAI[8]
General-Purpose Input and Output Port 3.0 (P3.0).
External Memory Interface (AD0).
PWM Phase 0 (PWM0).
Programmable Logic Array Input Element 8 (PLAI[8]).
32 P3.1/AD1/PWM1/PLAI[9]
General-Purpose Input and Output Port 3.1 (P3.1).
External Memory Interface (AD1).
PWM Phase 1 (PWM1).
Programmable Logic Array Input Element 9 (PLAI[9]).
33 P3.2/AD2/PWM2/PLAI[10]
General-Purpose Input and Output Port 3.2 (P3.2).
External Memory Interface (AD2).
PWM Phase 2 (PWM2).
Programmable Logic Array Input Element 10 (PLAI[10]).