Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 17 of 108
Pin No. Mnemonic Description
50 P1.1/SPM1/SOUT0/I2C0SDA/PLAI[1]
General-Purpose Input and Output Port 1.1 (P1.1).
Serial Port Multiplexed (SPM1).
UART download pin, UART0 Output (SOUT0).
I2C0 (I2C0SDA).
Programmable Logic Array Input Element 1 (PLAI[1]).
51 P1.0/T1/SPM0/SIN0/I2C0SCL/PLAI[0]
General-Purpose Input and Output Port 1.0 (P1.0).
Timer1 Input (T1).
Serial Port Multiplexed (SPM0).
UART download pin, UART0 Input (SIN0).
I2C0 (I2C0SCL).
Programmable Logic Array Input Element 0 (PLAI[0]).
52 P4.2/PLAO[10]
General-Purpose Input and Output Port 4.2 (P4.2).
Programmable Logic Array Output Element 10 (PLAO[10]).
53 P4.3/PLAO[11]
General-Purpose Input and Output Port 4.3 (P4.3).
Programmable Logic Array Output Element 11 (PLAO[11]).
54 P4.4/PLAO[12]
General-Purpose Input and Output Port 4.4 (P4.4).
Programmable Logic Array Output Element 12 (PLAO[12]).
55 RTCK JTAG Test Port Output, JTAG Return Test Clock.
56 V
REF
2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor when using
the internal reference.
57 DAC
REF
External Voltage Reference for the DACs. Range: DACGND to DACV
DD
.
58 AV
DD
3.3 V Analog Power.
59 AGND Analog Ground. Ground reference point for the analog circuitry.
60 GND
REF
Ground Voltage Reference for the ADC. For optimal performance, the analog power
supply should be separated from IOGND and DGND.
61 ADC0 Single-Ended or Differential Analog Input 0.
62 ADC1 Single-Ended or Differential Analog Input 1.
63 ADC2/CMP0
Single-Ended or Differential Analog Input 2 (ADC2).
Comparator Positive Input (CMP0).
64 ADC3/CMP1
Single-Ended or Differential Analog Input 3 (ADC3).
Comparator Negative Input (CMP1).