Datasheet
Data Sheet ADuC7124/ADuC7126
Rev. C | Page 101 of 108
HARDWARE DESIGN CONSIDERATIONS
POWER SUPPLIES
The ADuC7124/ADuC7126 operational power supply voltage
range is 2.7 V to 3.6 V. Separate analog and digital power supply
pins (AV
DD
and IOV
DD
, respectively) allow AV
DD
to be kept
relatively free of noisy digital signals often present on the
system IOV
DD
line. In this mode, the part can also operate with
split supplies; that is, it can use different voltage levels for each
supply. For example, the system can be designed to operate
with an IOV
DD
voltage level of 3.3 V while the AV
DD
level can be
at 3 V or vice versa. A typical split supply configuration is
shown in Figure 62.
09123-044
ADuC7124/
ADuC7126
0.1µF
ANALO
G
SUPPLY
10µF
AV
DD
DACV
DD
GND
REF
DACGND
AGND
IOV
DD
IOGND
0.1µF
+
–
DIGITAL
SUPPLY
10µF
+
–
Figure 62. External Dual Supply Connections
As an alternative to providing two separate power supplies, the
user can reduce noise on AV
DD
by placing a small series resistor
and/or ferrite bead between AV
DD
and IOV
DD
and then decoupling
AV
DD
separately to ground. An example of this configuration is
shown in Figure 63. With this configuration, other analog circuitry
(such as op amps, voltage reference, or any other analog circuitry)
can be powered from the AV
DD
supply line as well.
09123-145
ADuC7124/
ADuC7126
0.1µF
BEAD
AV
DD
AGND
IOV
DD
IOV
DD
IOV
DD
DGND
DGND
DGND
0.1µF
DIGITAL SUPPLY ANALOG SUPPLY
10µF
10µF
+
–
Figure 63. External Single Supply Connections
Notice that in both Figure 62 and Figure 63, a large value (10 µF)
reservoir capacitor sits on IOV
DD
, and a separate 10 µF capacitor
sits on AV
DD
. In addition, local small-value (0.1 µF) capacitors are
located at each AV
DD
and IOV
DD
pin of the chip. As per standard
design practice, be sure to include all of these capacitors and ensure
that the smaller capacitors are close to each AV
DD
pin with trace
lengths as short as possible. Connect the ground terminal of
each of these capacitors directly to the underlying ground plane.
Finally, note that the analog and digital ground pins on the
ADuC7124/ADuC7126 must be referenced to the same system
ground reference point at all times.
IOV
DD
Supply Sensitivity
The IOV
DD
supply is sensitive to high frequency noise because it
is the supply source for the internal oscillator and PLL circuits.
When the internal PLL loses lock, the clock source is removed
by a gating circuit from the CPU, and the ARM7TDMI core
stops executing code until the PLL regains lock. This feature
ensures that no flash interface timings or ARM7TDMI timings
are violated.
Typically, frequency noise greater than 50 kHz and 50 mV p-p
on top of the supply causes the core to stop working.
If decoupling values recommended in the Power Supplies
section do not sufficiently dampen all noise sources below
50 mV on IOV
DD
, a filter such as the one shown in Figure 64 is
recommended.
ADuC7124/
ADuC7126
IOV
DD
IOGND
0.1µF 0.1µF
DIGITAL
SUPPLY
10µF
+
–
1µH
09123-087
Figure 64. Recommended IOV
DD
Supply Filter
Linear Voltage Regulator
The ADuC7124/ADuC7126 require a single 3.3 V supply, but
the core logic requires a 2.6 V supply. An on-chip linear
regulator generates the 2.6 V from IOV
DD
for the core logic. The
LV
DD
pin is the 2.6 V supply for the core logic. An external
compensation capacitor of 0.47 µF must be connected between
LV
DD
and DGND (as close as possible to these pins) to act as a
tank of charge as shown in Figure 65.
09123-046
ADuC7124/
ADuC7126
0.47µF
LV
DD
DGND
Figure 65. Voltage Regulator Connections
The LV
DD
pin should not be used for any other chip. It is also
recommended to use excellent power supply decoupling on
IOV
DD
to help improve line regulation performance of the on-
chip voltage regulator.