Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 100 of 108
09123-042
DATAADDRESS
EXTRA ADDRESS
HOLD TIME
(BIT 10)
WRITE HOLD ADDRESS
AND DATA CYCLES
(BIT 8)
WRITE HOLD ADDRESS
AND DATA CYCLES
(BIT 8)
MCLK
AD[15:0]
MSx
AE
WS
Figure 60. External Memory Write Cycle with Address and Write Hold Cycles
0
9123-043
DATAADDRESS
1 WRITE STROBE WAIT STATE
(BIT 7 TO BIT 4)
1 ADDRESS WAIT STATE
(BIT 14 TO BIT 12)
MCLK
AD[15:0]
MSx
AE
WS
Figure 61. External Memory Write Cycle with Wait States