Datasheet

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 91 of 108
I
2
C Address 1, I2CADR1, Register
Name: I2CADR1
Address: 0xFFFF091C
Default value: 0x00
Access: Read and write
Function: This 8-bit MMR is used in 10-bit addressing
mode only. This register contains the least
significant byte of the address.
Table 102. I2CADR1 MMR in 10-Bit Address Mode
Bit Name Description
7:0
I2CLADR
These bits contain ADDR[7:0] in 10-bit
addressing mode.
I
2
C Master Clock Control, I2CDIV, Register
Name: I2CDIV
Address: 0xFFFF0924
Default value: 0x1F1F
Access: Read and write
Function: This MMR controls the frequency of the I
2
C
clock generated by the master on to the SCL
pin. For further details, see the Serial Clock
Generation section.
Table 103. I2CDIV MMR Bit Designations
Bit Name Description
15:8 DIVH These bits control the duration of the high
period of SCL.
7:0 DIVL These bits control the duration of the low period
of SCL.
I
2
C Slave Registers
I
2
C Slave Control, I2CSCON, Register
Name: I2CSCON
Address: 0xFFFF0928
Default value: 0x0000
Access: Read and write
Function: This 16-bit MMR configures the I
2
C peripheral
in slave mode.