Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
 
- Oscillator, PLL, and Power Control
- ADC Circuit Information- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
 
- Example Application Circuits
 
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator- Pulse-Width Modulator General Overview- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
 
 
- Pulse-Width Modulator General Overview
- UART Serial Interface- Baud Rate Generation
- UART Register Definitions
 
- I2C- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers- I2C Master Registers- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
 
- I2C Slave Registers
- I2C Common Registers
 
- I2C Master Registers
 
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

Data Sheet  ADuC7060/ADuC7061 
Rev. D | Page 83 of 108 
UART Control Register 1 
This 8-bit register controls the operation of the UART in 
conjunction with COMCON0. 
COMCON1 Register 
Name:  COMCON1 
Address:  0xFFFF0710 
Default value:  0x00 
Access:  Read and write 
Table 91. COMCON1 MMR Bit Designations 
Bit  Name  Description 
7:5    Reserved bits. Not used. 
4 
LOOPBACK 
Loopback. Set by user to enable 
loopback mode. In loopback mode, 
the transmit pin is forced high.  
3:2 
Reserved bits. Not used. 
1  RTS  Request to send. 
    Set by user to force the RTS output to 0. 
    Cleared by user to force the RTS 
output to 1. 
0  DTR  Data terminal ready.  
    Set by user to force the DTR output to 0. 
    Cleared by user to force the DTR 
output to 1. 
UART Status Register 0 
COMSTA0 Register 
Name:  COMSTA0 
Address:  0xFFFF0714 
Default value:  0x60 
Access:  Read only 
Function:  This 8-bit read-only register reflects the 
current status on the UART. 
Table 92. COMSTA0 MMR Bit Designations 
Bit  Name  Description 
7    Reserved. 
6 
TEMT 
COMTX and shift register empty status bit. 
    Set automatically if COMTX and the shift 
register are empty. This bit indicates that 
the data has been transmitted, that is, no 
more data is present in the shift register. 
Cleared automatically when writing to 
COMTX. 
5  THRE  COMTX empty status bit. 
Set automatically if COMTX is empty. 
COMTX can be written as soon as this bit 
is set; the previous data might not have 
been transmitted yet and can still be 
present in the shift register. 
    Cleared automatically when writing to 
COMTX. 
4  BI  Break indicator. 
Set when P1.0/IRQ1/SIN/T0 pin is held 
low for more than the maximum word 
length. 
    Cleared automatically. 
3  FE  Framing error. 
    Set when the stop bit is invalid. 
    Cleared automatically. 
2  PE  Parity error. 
    Set when a parity error occurs. 
    Cleared automatically. 
1  OE  Overrun error. 
    Set automatically if data is overwritten 
before being read. 
    Cleared automatically. 
0  DR  Data ready. 
    Set automatically when COMRX is full. 
    Cleared by reading COMRX. 










