Datasheet

Table Of Contents
ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 80 of 108
UART SERIAL INTERFACE
Each ADuC706x features a 16450-compatible UART. The
UART is a full-duplex, universal, asynchronous
receiver/transmitter. A UART performs serial-to-parallel
conversion on data characters received from a peripheral device
and parallel-to-serial conversion on data characters received from
the ARM7TDMI. The UART features a fractional divider that
facilitates high accuracy baud rate generation and a network
addressable mode. The UART functionality is available on the
P1.0/IRQ1/SIN/T0 and P1.1/SOUT pins of the ADuC706x.
The serial communication adopts an asynchronous protocol
that supports various word lengths, stop bits, and parity genera-
tion options selectable in the configuration register.
BAUD RATE GENERATION
The ADuC706x features two methods of generating the UART
baud rate: normal 450 UART baud rate generation and
ADuC706x fractional divider.
Normal 450 UART Baud Rate Generation
The baud rate is a divided version of the core clock using the
value in COMDIV0 and COMDIV1 MMRs (16-bit value,
divisor latch (DL)). The standard baud rate generator formula is
DL
RateBaud
××
=
216
MHz24.10
(1)
Table 88 lists common baud rate values.
Table 88. Baud Rate Using the Standard Baud Rate Generator
Baud Rate DL Actual Baud Rate % Error
9600 0x21 9696 1.01%
19,200 0x11 18,824 1.96%
115,200 0x3 106,667 7.41%
ADuC706x Fractional Divider
The fractional divider combined with the normal baud rate
generator allows the generation of accurate high speed baud rates.
/2
/(M + N/2048)
/16DL
UART
CORE
CLOCK
FBEN
07079-021
Figure 27. Fractional Divider Baud Rate Generation
Calculation of the baud rate using a fractional divider is as
follows:
)
2048
(216
MHz24.10
N
MDL
RateBaud
+×××
=
(2)
216
MHz24.10
2048 ×××
=+
DLRateBaud
N
M
Table 89 lists common baud rate values.
Table 89. Baud Rate Using the Fractional Baud Rate Generator
Baud Rate DL M N Actual Baud Rate % Error
9600 0x21 1 21 9598.55 0.015%
19,200 0x10 1 85 19,203 0.015%
115,200
0x2
1
796
115,218
0.015%
UART REGISTER DEFINITIONS
The UART interface consists of the following 11 registers:
COMTX: 8-bit transmit register
COMRX: 8-bit receive register
COMDIV0: divisor latch (low byte)
COMDIV1: divisor latch (high byte)
COMCON0: line control register
COMCON1: line control register
COMSTA0: line status register
COMSTA1: line status register
COMIEN0: interrupt enable register
COMIID0: interrupt identification register
COMDIV2: 16-bit fractional baud divide register
COMTX, COMRX, and COMDIV0 share the same address
location. COMTX and COMRX can be accessed when Bit 7 in
the COMCON0 register is cleared. COMDIV0 or COMDIV1
can be accessed when Bit 7 of COMCON0 or COMCON1,
respectively, is set.