Datasheet

Table Of Contents
ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 72 of 108
Timer2 Control Register
Name: T2CON
Address: 0xFFFF0368
Default value: 0x0000
Access: Read and write
Function: This 16-bit MMR configures the mode of operation of Timer2, as described in detail in Table 82.
Table 82. T2CON MMR Bit Designations
Bit Name Description
15:9 Reserved. These bits are reserved and should be written as 0 by user code.
8 T2DIR Count up/count down enable.
Set by user code to configure Timer2 to count up.
Cleared by user code to configure Timer2 to count down.
7 T2EN Timer2 enable.
Set by user code to enable Timer2.
Cleared by user code to disable Timer2.
6 T2MOD Timer2 operating mode.
Set by user code to configure Timer2 to operate in periodic mode.
Cleared by user to configure Timer2 to operate in free running mode.
5 WDOGMDEN Watchdog timer mode enable.
Set by user code to enable watchdog mode.
Cleared by user code to disable watchdog mode.
4 Reserved. This bit is reserved and should be written as 0 by user code.
3:2 T2SCALE Timer2 clock (32.768 kHz) prescaler.
00 = 32.768 kHz (default).
01 = source clock/16.
10 = source clock/256.
11 =
reserved.
1 WDOGENI Watchdog timer IRQ enable.
Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0.
Cleared by user code to disable the IRQ option.
0 T2PDOFF Stop Timer2 when power-down is enabled.
Set by user code to stop Timer2 when the peripherals are powered down using Bit 4 in the POWCON0 MMR.
Cleared by user code to enable Timer2 when the peripherals are powered down using Bit 4 in the
POWCON0 MMR.