Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 64 of 108
FIQSTAN
If IRQCONN[1] is asserted and FIQVEC is read, then one of
these bits asserts. The bit that asserts depends on the priority of
the FIQ. If the FIQ is of Priority 0, Bit 0 asserts; Priority 1, Bit 1
asserts; and so forth.
When a bit is set in this register, all interrupts of that priority
and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is possible to clear only one bit as a time. For
example, if this register is set to 0x09, writing 0xFF changes the
register to 0x08, and writing 0xFF a second time changes the
register to 0x00.
FIQSTAN Register
Name: FIQSTAN
Address: 0xFFFF013C
Default value: 0x00000000
Access: Read and write
Table 75. FIQSTAN MMR Bit Designations
Bit
Name
Description
31:8 Reserved These bits are reserved and should not be
written to.
7:0 Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
External Interrupts (IRQ0 to IRQ3)
The ADuC706x provides up to four external interrupt sources.
These external interrupts can be individually configured as level
triggered or rising/falling edge triggered.
To enable the external interrupt source, the appropriate bit must
first be set in the FIQEN or IRQEN register. To select the
required edge or level to trigger on, the IRQCONE register
must be appropriately configured.
To properly clear an edge based external IRQ interrupt, set the
appropriate bit in the IRQCLRE register.
IRQCONE Register
Name: IRQCONE
Address: 0xFFFF0034
Default value: 0x00000000
Access: Read and write
Table 76. IRQCONE MMR Bit Designations
Bit
Name
Description
31:8 Reserved These bits are reserved and should not be written to.
7:6 IRQ3SRC[1:0] [11] = External IRQ3 triggers on falling edge.
[10] = External IRQ3 triggers on rising edge.
[01] = External IRQ3 triggers on low level.
[00] = External IRQ3 triggers on high level.
5:4 IRQ2SRC[1:0] [11] = External IRQ2 triggers on falling edge.
[10] = External IRQ2 triggers on rising edge.
[01] = External IRQ2 triggers on low level.
[00] = External IRQ2 triggers on high level.
3:2 IRQ1SRC[1:0] [11] = External IRQ1 triggers on falling edge.
[10] = External IRQ1 triggers on rising edge.
[01] = External IRQ1 triggers on low level.
[00] = External IRQ1 triggers on high level.
1:0 IRQ0SRC[1:0] [11] = External IRQ0 triggers on falling edge.
[10] = External IRQ0 triggers on rising edge.
[01] = External IRQ0 triggers on low level.
[00] = External IRQ0 triggers on high level.