Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 45 of 108
Table 43. ADC0CON MMR Bit Designations
Bit Name Description
15 ADC0EN Primary channel ADC enable.
This bit is set to 1 by user code to enable the primary ADC.
Clearing this bit to 0 powers down the primary ADC and resets the respective ADC ready bit in the ADCSTA MMR
to 0.
14:13 ADC0DIAG[1:0] Diagnostic current source enable bits.
[00] = current sources off.
[01] = enables a 50 μA current source on the selected positive input (for example, ADC0).
[10] = enables a 50 μA current source on the selected negative input (for example, ADC1).
[11] = enables a 50 μA current source on both selected inputs (for example, ADC0 and ADC1).
12
HIGHEXTREF0
This bit must be set high if the external reference for ADC0 exceeds 1.35 V. This results in the reference source
being divided by 2.
Clear this bit when using the internal reference or an external reference of less than 1.35 V.
11 AMP_CM This bit is set to 1 by user to set the PGA output common-mode voltage to AVDD/2.
This bit is cleared to 0 by user code to set the PGA output common-mode voltage to the PGA input common-
mode voltage level.
10 ADC0CODE Primary channel ADC output coding.
This bit is set to 1 by user code to configure primary ADC output coding as unipolar.
This bit is cleared to 0 by user code to configure primary ADC output coding as twos complement.
9:6 ADC0CH[3:0] Primary channel ADC input select.
[0000] = ADC0/ADC1 (differential mode).
[0001] = ADC0/ADC5 (single-ended mode).
[0010] = ADC1/ADC5 (single-ended mode).
[0011] = VREF+, VREF−. Note: This is the reference selected by the ADC0REF bits.
[0100] = Not used. This bit combination is reserved for future functionality and should not be written.
[0101] = ADC2/ADC3 (differential mode).
[0110] = ADC2/ADC5 (single-ended mode).
[0111] = ADC3/ADC5 (single-ended mode).
[1000] = internal short to ADC1.
[1001] = internal short to ADC1.
5:4 ADC0REF[1:0] Primary channel ADC reference select.
[00] = internal reference selected. In ADC low power mode, the voltage reference selection is controlled by
ADCMDE[5].
[01] = external reference inputs (VREF+, VREF−) selected. Set the HIGHEXTREF0 bit if the reference voltage
exceeds 1.3 V.
[10] = auxiliary external reference inputs (ADC4/EXT_REF2IN+, ADC5/EXT_REF2IN−) selected. Set the
HIGHEXTREF0 bit if the reference voltage exceeds 1.3 V.
[11] = (AVDD, AGND) divide-by-two selected.
3:0 ADC0PGA[3:0]. Primary channel ADC gain select. Note, nominal primary ADC full-scale input voltage = (VREF/gain).
[0000] = ADC0 gain of 1. Buffer of negative input is bypassed.
[0001] = ADC0 gain of 2.
[0010] = ADC0 gain of 4 (default value). Enables the in-amp.
[0011] = ADC0 gain of 8.
[0100] = ADC0 gain of 16.
[0101] = ADC0 gain of 32.
[0110] = ADC0 gain of 64 (maximum PGA gain setting).
[0111] = ADC0 gain of 128 (extra gain implemented digitally).
[1000] = ADC0 gain of 256.
[1001] = ADC0 gain of 512.
[1XXX] = ADC0 gain is undefined.