Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 94 of 108
Bit Name Description
2 I2CSTXQ I
2
C slave transmit request bit.
This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in I2CSCON
is =0, this bit goes high just after the negative edge of SCL during the read bit transmission. If the I2CSETEN bit in
I2CSCON is =1, this bit goes high just after the positive edge of SCL during the read bit transmission. This bit
causes an interrupt to occur if the I2CSTXENI bit in I2CSCON is set.
This bit is cleared in all other conditions.
1 I2CSTFE I
2
C slave FIFO underflow status bit.
This bit goes high if the transmit FIFO is empty when a master requests data from the slave. This bit is asserted at
the rising edge of SCL during the read bit.
This bit is cleared in all other conditions.
0 I2CETSTA I
2
C slave early transmit FIFO status bit.
If the I2CSETEN bit in I2CSCON is =0, this bit goes high if the slave transmit FIFO is empty. If the I2CSETEN bit in
I2CSCON = 1, this bit goes high just after the positive edge of SCL during the write bit transmission. This bit
asserts once only for a transfer.
This bit is cleared after being read.
I
2
C Slave Receive, I2CSRX, Register
Name: I2CSRX
Address: 0xFFFF0930
Default value: 0x00
Access: Read only
Function: This 8-bit MMR is the I
2
C slave receive register.
I
2
C Slave Transmit, I2CSTX, Register
Name: I2CSTX
Address: 0xFFFF0934
Default value: 0x00
Access: Write only
Function: This 8-bit MMR is the I
2
C slave transmit
register.
I
2
C Hardware General Call Recognition, I2CALT, Register
Name: I2CALT
Address: 0xFFFF0938
Default value: 0x00
Access: Read and write
Function: This 8-bit MMR is used with hardware general
calls when the I2CSCON Bit 3 is set to 1. This
register is used in cases where a master is
unable to generate an address for a slave and,
instead, the slave must generate the address for
the master.
I
2
C Slave Device ID, I2CIDx, Registers
Name: I2CIDx
Addresses: 0xFFFF093C = I2CID0
0xFFFF0940 = I2CID1
0xFFFF0944 = I2CID2
0xFFFF0948 = I2CID3
Default value: 0x00
Access: Read and write
Function: These 8-bit MMRs are programmed with the
I
2
C bus IDs of the slave. See the I2C Bus
Addresses section for further details.