Datasheet

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 93 of 108
I
2
C Slave Status, I2CSSTA, Register
Name: I2CSSTA
Address: 0xFFFF092C
Default value: 0x0000
Access: Read and write
Function: This 16-bit MMR is the I
2
C status register in slave mode.
Table 105. I2CSSTA MMR Bit Designations
Bit
Name
Description
15 Reserved bit.
14 I2CSTA This bit is set to 1 if
a start condition followed by a matching address is detected, a start byte (0x01) is received, or
general calls are enabled and a general call code of 0x00 is received.
This bit is cleared on receiving a stop condition
13 I2CREPS This bit is set to 1 if a repeated start condition is detected.
This bit is cleared on receiving a stop condition.
12:11 I2CID[1:0] I
2
C address matching register. These bits indicate which I2CIDx register matches the received address.
[00] = received address matches I2CID0.
[01] = received address matches I2CID1.
[10] = received address matches I2CID2.
[11] = received address matches I2CID3.
10 I2CSS I
2
C stop condition after start detected bit.
This bit is set to 1 when a stop condition is detected after a previous start and matching address. When the
I2CSSENI bit in I2CSCON is set, an interrupt is generated.
This bit is cleared by reading this register.
9:8
I2CGCID[1:0]
I
2
C general call ID bits.
[00] = no general call received.
[01] = general call reset and program address.
[10] = general program address.
[11] = general call matching alternative ID.
Note that these bits are not cleared by a general call reset command.
Clear these bits by writing a 1 to the I2CGCCLR bit in I2CSCON.
7 I2CGC I
2
C general call status bit.
This bit is set to 1 if the slave receives a general call command of any type. If the command received was a reset
command, then all registers return to their default states. If the command received was a hardware general call,
the receive FIFO holds the second byte of the command, and this can be compared with the I2CALT register.
Clear this bit by writing a 1 to the I2CGCCLR bit in I2CSCON.
6 I2CSBUSY I
2
C slave busy status bit.
Set to 1 when the slave receives a start condition.
Cleared by hardware if the received address does not match any of the I2CIDx registers, the slave device receives
a stop condition, or a repeated start address does not match any of the I2CIDx registers.
5 I2CSNA I
2
C slave no acknowledge data bit.
This bit is set to 1 when the slave responds to a bus address with a no acknowledge. This bit is asserted under the
following conditions: if a no acknowledge was returned because there was no data in the transmit FIFO or if the
I2CNACKEN bit was set in the I2CSCON register.
This bit is cleared in all other conditions.
4 I2CSRxFO Slave receive FIFO overflow.
This bit is set to 1 when a byte is written to the receive FIFO when it is already full.
This bit is cleared in all other conditions.
3 I2CSRXQ I
2
C slave receive request bit.
This bit is set to 1 when the receive FIFO of the slave is not empty. This bit causes an interrupt to occur if the
I2CSRXENI bit in I2CSCON is set.
The receive FIFO must be read or flushed to clear this bit.