Datasheet

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 87 of 108
SERIAL CLOCK GENERATION
The I
2
C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
The bit rate is defined in the I2CDIV MMR as follows:
) (2 )2( DIVLDIVH +++
=
UCLK
CLOCKSERIAL
f
f
where:
f
UCLK
is the clock before the clock divider.
DIVH is the high period of the clock.
DIVL is the low period of the clock.
Thus, for 100 kHz operation
DIVH = DIVL = 0x33
and for 400 kHz
DIVH = 0x0A, DIVL = 0x0F
The I2CDIV register corresponds to DIVH:DIVL.
I
2
C BUS ADDRESSES
Slave Mode
In slave mode, the I2CID0, I2CID1, I2CID2, and I2CID3
registers contain the device IDs. The device compares the four
I2CIDx registers to the address byte received from the bus
master. To be correctly addressed, the 7 MSBs of any ID register
must be identical to the 7 MSBs of the first received address
byte. The least significant bit of the ID registers (the transfer
direction bit) is ignored in the process of address recognition.
The ADuC706x also supports 10-bit addressing mode. When
Bit 1 of I2CSCON (ADR10EN bit) is set to 1, then one 10-bit
address is supported in slave mode and is stored in the I2CID0
and I2CID1 registers. The 10-bit address is derived as follows:
I2CID0[0] is the read/write bit and is not part of the I
2
C
address.
I2CID0[7:1] = Address Bits[6:0].
I2CID1[2:0] = Address Bits[9:7].
I2CID1[7:3] must be set to 11110b.
Master Mode
In master mode, the I2CADR0 register is programmed with the
I
2
C address of the device.
In 7-bit address mode, I2CADR0[7:1] are set to the device
address. I2CADR0[0] is the read/write bit.
In 10-bit address mode, the 10-bit address is created as follows:
I2CADR0[7:3] must be set to 11110b.
I2CADR0[2:1] = Address Bits[9:8].
I2CADR1[7:0] = Address Bits[7:0].
I2CADR0[0] is the read/write bit.
I
2
C REGISTERS
The I
2
C peripheral interface consists overall of 19 MMRs. Nine
of these are master related only, nine are slave related only, and
one MMR is common to both master and slave modes.
I
2
C Master Registers
I
2
C Master Control, I2CMCON Register
Name: I2CMCON
Address: 0xFFFF0900
Default
value:
0x0000
Access: Read and write
Function: This 16-bit MMR configures the I
2
C peripheral in
master mode.