Datasheet

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 86 of 108
I
2
C
Each ADuC706x incorporates an I
2
C peripheral that can be
configured as a fully I
2
C-compatible I
2
C bus master device or
as a fully I
2
C bus-compatible slave device. The two pins used for
data transfer, SDA and SCL, are configured in a wire-AND’e d
format that allows arbitration in a multimaster system. These
pins require external pull-up resistors. Typical pull-up resistor
values are between 4.7 kΩ and 10 kΩ.
Users program the I
2
C bus peripheral (addressed in the I
2
C bus
system). This ID can be modified any time that a transfer is not
in progress. The user can configure the interface to respond to
four slave addresses.
The transfer sequence of an I
2
C system consists of a master
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the slave device address
and the direction of the data transfer (read or
write
) during the
initial address transfer. If the master does not lose arbitration
and the slave acknowledges, the data transfer is initiated. This
continues until the master issues a stop condition and the bus
becomes idle.
The I
2
C peripheral can be configured only as a master or a slave
at any given time. The same I
2
C channel cannot simultaneously
support master and slave modes.
The I
2
C interface on the ADuC706x includes the following
features:
• Support for repeated start conditions. In master mode, the
ADuC706x can be programmed to generate a repeated
start. In slave mode, the ADuC706x recognizes repeated
start conditions.
• In master and slave modes, the part recognizes both 7-bit
and 10-bit bus addresses.
• In I
2
C master mode, the ADuC706x supports continuous
reads from a single slave up to 512 bytes in a single transfer
sequence.
• Clock stretching is supported in both master and slave
modes.
• In slave mode, the ADuC706x can be programmed to
return a no acknowledge (NACK). This allows the
validation of checksum bytes at the end of I
2
C transfers.
• Bus arbitration in master mode is supported.
• Internal and external loopback modes are supported for
I
2
C hardware testing.
• The transmit and receive circuits in both master and slave
modes contain 2-byte FIFOs. Status bits are available to the
user to control these FIFOs.
CONFIGURING EXTERNAL PINS FOR I
2
C
FUNCTIONALITY
The I
2
C functions of the P0.1/SCLK/SCL and P0.3/MOSI/SDA
pins of the ADuC706x device are P0.1 and P0.3. The function of
P0.1 is the I
2
C clock signal (SCL) and the function of P0.3 is the
I
2
C data signal (SDA). To configure P0.1 and P0.3 for I
2
C mode,
Bit 4 and Bit 12 of the GP0CON0 register must be set to 1. Bit 1
of the GP0CON1 register must also be set to 1 to enable I
2
C
mode.
Note that, to write to GP0CON1, the GP0KEY1 register must
be set to 0x7 immediately before writing to GP0CON1. Also,
the GP0KEY2 register must be set to 0x13 immediately after
writing to GP0CON1. The following code example shows this
in detail:
GP0CON0 = BIT4 + BIT12; // Select SPI/I
2
C alternative function for P0.1 and P0.3
GP0KEY1 = 0x7; // Write to GP0KEY1
GP0CON1 = BIT1; // Select I
2
C functionality for P0.1 and P0.3
GP0KEY2 = 0x13; // Write to GP0KEY2