Datasheet

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 8 of 108
Parameter Test Conditions/Comments Min Typ Max Unit
EXCITATION CURRENT SOURCES
Output Current Available from each current
source
200 1000 μA
Initial Tolerance at 25°C ±5 %
Drift
1
0.06 %/°C
Initial Current Matching at 25°C Matching between both current
sources
±0.5 %
Drift Matching
1
20 ppm/°C
Line Regulation (AVDD)
1
AVDD = 2.5 V ± 5% 0.2 %/V
Output Compliance
1
AVDD − 0.7 V AGND − 30 mV V
WATCHDOG TIMER (WDT)
Timeout Period
1
32.768 kHz clock, 256 prescale 0.008 512 sec
Timeout Step Size 7.8 ms
FLASH/EE MEMORY
1
Endurance
16
10,000 Cycles
Data Retention
17
20 Years
DIGITAL INPUTS All digital inputs except NTRST
Input Leakage Current Input (high) = DVDD ±1 ±10 µA
Input Pull-Up Current Input (low) = 0 V 10 20 80 µA
Input Capacitance 10 pF
Input Leakage Current NTRST only: input (low) = 0 V ±1 ±10 µA
Input Pull-Down Current NTRST only: input (high) = DVDD 30 55 100 µA
LOGIC INPUTS
1
All logic inputs
Input Low Voltage (VINL) 0.4 V
Input High Voltage (VINH) 2.0 V
LOGIC OUTPUTS
1
All logic outputs except XTALO
Output Low Voltage (VOL) I
SOURCE
= 1.6 mA 0.6 V
Output High Voltage (VOH) I
SOURCE
= 1.6 mA 2.0 V
CRYSTAL OSCILLATOR
1
Logic Inputs, XTALI Only
Input Low Voltage (VINL) 0.8 V
Input High Voltage (VINH) 1.7 V
XTALI Capacitance 12 pF
XTALO Capacitance 12 pF
ON-CHIP OSCILLATORS
Oscillator
32,768
kHz
Accuracy −3 +3 %
MCU CLOCK RATE Eight programmable core clock
selections within this range:
binary divisions 1, 2, 4, 8 . . . 64, 128
0.08 1.28 10.24 MHz
Using an External Clock to
P2.0/EXTCLK Pin
0.08 10.24 MHz
MCU START-UP TIME
At Power-On Includes kernel power-on
execution time
134 ms
After Reset Event Includes kernel power-on
execution time
5 ms
From MCU Power-Down
PLL On
Wake-Up from Interrupt CD = 0 4.8 μs
PLL Off
Wake-Up from Interrupt CD = 0 66 μs
Internal PLL Lock Time
1
ms