Datasheet

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Table Of Contents

Features
Applications
General Description
Revision History
Functional Block Diagram
Specifications
- Electrical Specifications
- Timing Specifications
  - I2C Timing
  - SPI Timing
Absolute Maximum Ratings
- ESD Caution
Pin Configurations and Function Descriptions
Terminology
Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
  - ARM7 Exceptions
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
  - RSTSTA Register
  - RSTCLR Register
Oscillator, PLL, and Power Control
- Clocking System
  - External Crystal Selection
  - External Clock Selection
- Power Control System
  - Power and Clock Control Registers
ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- Example Application Circuits
DAC Peripherals
- DAC
  - Op Amp Mode
- MMR Interface
  - DAC0CON Register
  - DAC0DAT Register
- Using the DAC
Nonvolatile Flash/EE Memory
- Flash/EE Memory Reliability
- Programming
  - Serial Downloading (In-Circuit Programming)
  - JTAG Access
Processor Reference Peripherals
- Interrupt System
- IRQ
- Fast Interrupt Request (FIQ)
- Programmed Interrupts
  - SWICFG
    - SWICFG Register
- Vectored Interrupt Controller (VIC)
- VIC MMRs
Timers
- HR:MIN:SEC: 1/128 Format
- Timer0
- Timer1 or Wake-Up Timer
- Timer2 or Watchdog Timer
- Timer3
Pulse-Width Modulator
- Pulse-Width Modulator General Overview
UART Serial Interface
- Baud Rate Generation
  - Normal 450 UART Baud Rate Generation
  - ADuC706x Fractional Divider
- UART Register Definitions
I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
  - Slave Mode
  - Master Mode
- I2C Registers
Serial Peripheral Interface
- MISO (Master In, Slave Out) Pin
- MOSI (Master Out, Slave In) Pin
- SCLK (Serial Clock I/O) Pin
- Slave Select (P0.0/) Input Pin
- Configuring External Pins for SPI Functionality
- SPI Registers
General-Purpose I/O
- GPxCON Registers
- GPxDAT Registers
- GPxSET Registers
- GPxCLR Registers
- GPxPAR Registers
  - GP0CON1 Control Registers
Hardware Design Considerations
- Power Supplies
Outline Dimensions
- Ordering Guide

Data Sheet ADuC7060/ADuC7061

Rev. D | Page 77 of 108

On power-up, PWMCON defaults to 0x0012 (HOFF = 1 and

HMODE = 1). All GPIO pins associated with the PWM are

configured in PWM mode by default (seeTable 86). Clear the

PWM trip interrupt by writing any value to the PWMCLRI

MMR. Note that when using the PWM trip interrupt, clear the

PWM interrupt before exiting the ISR. This prevents generation

of multiple interrupts.

Table 86. PWM Output Selection

PWMCON MMR

PWM Outputs

ENA HOFF POINV DIR PWM0 PWM1 PWM2 PWM3

0 0 X X 1 1 1 1

X 1 X X 1 0 1 0

1 0 0 0 0 0 HS1 LS1

1 0 0 1 HS1 LS1 0 0

1 0 1 0 HS1 LS1 1 1

1 0 1 1 1 1 HS1 LS1

X is don’t care.

HS = high side, LS = low side.

Table 87. Compare Registers

Name Address Default Value Access

PWM0COM0 0xFFFF0F84 0x0000 R/W

PWM0COM1 0xFFFF0F88 0x0000 R/W

PWM0COM2 0xFFFF0F8C 0x0000 R/W

PWM1COM0 0xFFFF0F94 0x0000 R/W

PWM1COM1 0xFFFF0F98 0x0000 R/W

PWM1COM2 0xFFFF0F9C 0x0000 R/W

PWM2COM0 0xFFFF0FA4 0x0000 R/W

PWM2COM1

0xFFFF0FA8

0x0000

R/W

PWM2COM2 0xFFFF0FAC 0x0000 R/W